Every lesson in the Analog CMOS IC Design slide course, in full text: 7 decks, 375 slides.
HW2 · DC Bias: Currents & Saturation (Baker 20.25, 20.45)Part 1 of 2 for ENEE 411 Homework 2. It works the two DC-operating-point problems end to end using the Baker long-channel process. In Problem 20.25 you trace VSG through a PMOS mirror to find the current in M3, which comes out at 10 uA to first order and about 11 uA once channel-length modulation is included. In Problem 20.45 you solve the reference-branch KVL quadratic for the bias current (about 29.6 uA), find every node voltage, and derive the largest R2 that still keeps the cascode M4 in saturation - about 127 kohm, which means the given 125 kohm sits right at the edge. The 23 slides include schematic SVGs, a table separating the stated parameters from the corrected ones, two traps, and two checks.
HW2 · Small-Signal Gain & Frequency Response (Baker 21.7, 21.26, 21.30, 21.36)Part 2 of 2 for ENEE 411 Homework 2, covering the four small-signal problems. Every DC bias is set at 20 uA, so gm is 155 uA/V and ro is 833 k throughout. Problem 21.26 derives the common-gate gain, (1/gmp||rop||ron)/(1/gmn||ron), which reduces to roughly gmn/gmp and therefore to about 1. Problem 21.30 works out the cascode amplifier's three gains: vd1b/vin is about -1 because the cascode node hides the gain, vout/vd1b is about +8300, and vout/vin is about -8300, or 78 dB. Problem 21.7 finds a common-source stage's midband gain and the low-frequency high-pass corner set by the large coupling capacitor. Problem 21.36 gives a midband gain of about 128 (42 dB), a high-frequency pole near 19 kHz from the 10 pF load, an output of about 25 mV, inverted, for a 1 MHz 10 mV drive, and a unity-gain frequency fu = gm/(2*pi*CL) of about 2.47 MHz. The 38 slides include schematic, Bode, and waveform SVGs, four traps, four checks, and a SPICE-verification slide.
HW3 · P1: Differential Amplifier (Baker 22.16)ENEE 411 Homework 3, Problem 1 (Baker 22.16), worked on long-channel Table 9.1. The 5-transistor OTA - an NMOS pair at 10/2, a PMOS active-mirror load at 20/2, and a 10 uA tail - is worked through in full course notation. Part (a) finds the DC operating point at VCM = VDD/2: ID = 5 uA per branch, Vov_n = 0.129 V with VGS = 0.929 V, Vov_p = 0.158 V with VSG = 1.058 V, VS = 1.571 V, plus every node voltage and every saturation check. Part (b) gets the gain from the differential half-circuit, deriving gm1 = 77.5 uA/V, ro2 = 20 M, ro4 = 16 M, and Av = gm1(ro2||ro4) = 690, or 57 dB, with the AC current directions shown. Part (c) fixes the common-mode range, running from a VCM,min of about 2.1 V, since the cascode tail needs VTHN + 2Vov,tail of headroom, up to VCM,max = Vout + VTHN of about 4.74 V. Part (d) gives f3dB = 1/(2pi*Rout*CL) of about 1.8 kHz and fu = gm1/(2pi*CL) of about 1.23 MHz, which is independent of lambda. The 34 slides use real MOSFET-symbol schematics, half-circuit and Bode figures, the body-effect caveat on hand analysis versus SPICE, three traps, and two checks.
HW3 · P2: Two-Stage Op-Amp (Baker Example)ENEE 411 Homework 3, Problem 2, which describes how the two-stage Miller op-amp operates on short-channel Table 9.2 at VDD = 1 V in a 50 nm process. Stage 1 is the NMOS pair M1/M2 with the PMOS active mirror M3/M4, biased by the cascode tail M6T/M6B; the mirror folds both currents so Gm1 = gm1, giving Av1 = gm1*(ro2||ro4). Stage 2 is a PMOS common-source device M7 with an NMOS cascode sink M8T/M8B, whose high output resistance leaves Rout2 at roughly ro7, so Av2 = gm7*ro7 is about 50, the PMOS intrinsic gain. With the Table 9.2 values (gm = 150 uA/V, ron = 167 k, rop = 333 k), stage 1 comes out near 17 with the simple mirror and stage 2 near 50 with the cascode load, for a total open-loop gain of about 835, or roughly 58 dB. The Miller capacitor Cc splits the poles and sets the dominant one, with fun = gm1/(2pi*Cc), and the nulling resistor Rz = 1/gm7, about 6.7 k, cancels the right-half-plane zero. The 24 slides include a real MOSFET-symbol schematic, a pole-splitting figure, a SPICE .ac and .tran plan, three traps, and two checks.
HW3 · P3: Three-Stage Op-Amp (Baker 24.24)ENEE 411 Homework 3, Problem 3 (Baker 24.24), rebuilt in full course notation on short-channel Table 9.2 at VDD = 1 V in a 50 nm process. The circuit is three cascaded gain stages with nested-Miller compensation, using Cc1 = 240 f and Cc2. Part (a) finds the open-loop DC gain AOLDC = Av1*Av2*Av3, where each stage contributes roughly gm*Rnode and the intrinsic gain gm*ro is 25 or 50, so the total reaches several thousand - about 74 dB with no load capacitor. It then finds the 3 dB cutoff at each internal node, f3dB,k = 1/(2pi*Rk*Ck) for nodes 1, 2, and 3, where the lowest is the dominant pole, and compares the result with SPICE. Part (b) runs AC and transient analysis with a 100 fF load and demonstrates supply-independent biasing: a self-biased cascode reference holds IVDD nearly constant between VDD = 1 V and 1.2 V in the unity-gain configuration. The 18 slides include block-diagram and nested-Miller figures, three traps, two checks, and a SPICE .op, .ac, and .tran plan.
HW3 · P4: Voltage at Point A (Baker 10.14)ENEE 411 Homework 3, Problem 4 (Baker 10.14), rebuilt in full course notation on long-channel Table 9.1 and Lecture 10, the MOSFET pass gate. Two rules drive everything: an NMOS pass gate passes a good 0 but loses a threshold on a 1, stopping at VDD - VTHN = 4.2 V, while a PMOS pass gate passes a good 1 but loses a drop on a 0, stopping at |VTHP| = 0.9 V. Pass gates in series stack their drops, giving VDD - 2VTHN, and an NMOS high is limited by its gate rather than its drain, which is why circuit (g) still stops at 4.2 V even with 3*VDD on the drain. Circuits (a), (b), and (g) are transmission gates with both gates at VDD, so only the NMOS conducts. The deck closes with a results table for (a) through (g) - 4.2, 0, 0, 4.2, 0.9, 5, and 4.2 V - and a SPICE .op verification. Its 19 slides include pass-gate threshold-drop figures, three traps, and two checks.
HW3 · P5: Inverter VTC & Delays (Baker 11.14)ENEE 411 Homework 3, Problem 5 (Baker 11.14), rebuilt in full course notation on long-channel Table 9.1 and Lecture 11, covering two ratioed (non-complementary) inverters. Part (a) derives the square-law VTC: at VSP both devices are saturated with equal drain currents, so the switching point follows from sqrt(betaD/betaL). The NMOS-load inverter degrades the high output, with VOH = VDD - VTHN = 4.2 V, VOL about 0.36 V, and VSP about 1.85 V; the PMOS-load inverter degrades the low output instead, with VOL = |VTHP| = 0.9 V, VOH about 4.64 V, and VSP about 3.11 V. Part (b) finds the delays into a 100 fF load using the digital resistor model t = 0.7*R*Ctot: a strong driver takes about 17 ps while a weak load takes 80 to 150 ps, which makes tPHL and tPLH asymmetric and gives the 4-to-1 rule, tLH > tHL. The 21 slides use real MOSFET-symbol inverter schematics, VTC and waveform figures, three traps, two checks, and a SPICE VTC and .tran plan.
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