HW3 · P5: Inverter VTC & Delays (Baker 11.14)

Discussion prompt

Before we open HW3 · P5: Inverter VTC & Delays (Baker 11.14): without looking back, what was the main idea of HW3 · P4: Voltage at Point A (Baker 10.14), and what could you do by the end of it that you could not do before?

Hint: One sentence for the idea, one for the skill. If the second one is blank, that is the part to revisit.

Comparison matrix

From Process & device sizes: refill the value column from what you know. The rest of the table is as it appeared.

Discussion prompt

In both, the load is always on and the driver is input-controlled - so the output is a tug-of-war set by the size ratio. That is ratioed logic.

That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.

Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.

Discussion prompt

At any operating point the load current = driver current. Choosing each device's region (triode vs saturation) and equating currents is the whole VTC method (Lecture 11).

That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.

Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.

Discussion prompt

Run Recipe: VOH, VOL, and VSP with this step confiscated:

VSP: at In = Out = VSP both devices are saturated; equate the two saturation currents.

Is it still possible? If it is, say what takes its place and what it costs you. If it is not, say exactly what that step was providing that nothing else does.

Hint: A step you can drop for free was never load-bearing. If you cannot drop it, name the thing that goes wrong the moment it is gone.

Discussion prompt

Recipe: VOH, VOL, and VSP works on the cases you have just seen. Push it to the edge: what is the most degenerate input it still handles — empty, zero, one item, everything equal — and what is the first case where it stops being true? Name the case, not just "it breaks".

Hint: Try the smallest legal input, then the largest, then the one where two things collide. Methods are specified at their edges; the middle takes care of itself.

Predict first

Drive In low so the driver is off; the NMOS load pulls Out up. An NMOS load (gate at VDD) shuts off once its source reaches one threshold below its gate:

Commit before you compute: what does (a) VOH - the load gives up the high come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.

Correct: Note the body effect

Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. The load's source rises to ~4.2 V, so its VTHN actually increases - the real VOH is a bit below 4.2 V.

Animation

Shows: Each line of the worked example "(a) VOH - the load gives up the high", appearing one at a time.

The same working the example does, in the order a tutor would write it.

Takeaway: The load's source rises to ~4.2 V, so its VTHN actually increases - the real VOH is a bit below 4.2 V. SPICE gives the exact value.

Discussion prompt

Drive In = VDD. The driver (10/1) is in triode at small Out; the load (10/5) is in saturation. Set the two currents equal:

What do you need to know — or decide — before the first line can be written? List everything the problem has to hand you.

Hint: Anything you would have to invent to get started is a thing the problem must supply.

Animation

Shows: Each line of the worked example "(a) VOL - the strong driver wins", appearing one at a time.

The same working the example does, in the order a tutor would write it.

Takeaway: With the 5:1 strength ratio the small-VOL solution is about 0.36 V - not a clean logic 0. Ratioed logic always has a nonzero VOL.

Fill in the blanks

From (a) VSP - both devices saturated — finish the line. Write what belongs on the right of the equals sign before you look.

\sqrt(V_{DD}-V_{SP}-V_{THN})___}\,(V____-V____) = ___

Why: Producing the right-hand side unprompted is the difference between recognising this line and being able to use it. 2.236(VSP - 0.8) = 4.2 - VSP -> 3.236*VSP = 5.989 -> VSP = 1.85 V.

Animation

Shows: Each line of the worked example "(a) VSP - both devices saturated", appearing one at a time.

The same working the example does, in the order a tutor would write it.

Takeaway: 2.236(VSP - 0.8) = 4.2 - VSP -> 3.236*VSP = 5.989 -> VSP = 1.85 V. The strong driver pulls the trip point well below mid-rail.

Predict first

A student writes this, and it looks reasonable:

Reading the NMOS-load inverter like a CMOS inverter and writing VOH = VDD = 5 V.

It is wrong. Say what breaks — and say it before you turn the page.

Correct: An NMOS load cannot pass a clean high - it shuts off one VTHN below its gate.

Ask what rail the load can actually deliver.

Why: An NMOS load cannot pass a clean high - it shuts off one VTHN below its gate. The output never reaches 5 V.

Discussion prompt

The rule this trap just fixed:

The always-on NMOS load gives up one threshold on the high side. (A PMOS load does the same to the LOW side.)

Now break it on purpose. Build a case that violates it and follow the consequences until something visibly fails. Where does the failure first show up — and would you have noticed it if you had not been looking?

Hint: The dangerous rules are the ones whose violation still produces an answer. If yours fails loudly, try to find one that fails quietly.

Predict first

Now the always-on load is a PMOS (gate at GND). It cannot pull Out below one threshold above ground, so the low is the degraded rail:

Commit before you compute: what does (a) The PMOS-load inverter is the dual come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.

Correct: Switching point

Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. Both PMOS saturated at VSP: 2.236(VDD - VSP - 0.9) = (VSP - 0.9) -> VSP ~ 3.11 V, pushed above mid-rail (mirror image of the NMOS-load case).

Annotate

From (a) The PMOS-load inverter is the dual — read this one piece at a time. What is each part doing?

On: \( V_{OL}=|V_{THP}|=0.9\,\text{V} \)

• When In = 0 the strong PMOS driver (10/1) pulls up against the weak PMOS load (10/5). By the same ratio math, VOH ~ VDD - 0.36 = 4.64 V.
• Both PMOS saturated at VSP: 2.236(VDD - VSP - 0.9) = (VSP - 0.9) -> VSP ~ 3.11 V, pushed above mid-rail (mirror image of the NMOS-load case).

Comparison matrix

From Both inverters at a glance: refill the VOL column from what you know. The rest of the table is as it appeared.

Discussion prompt

Lecture 10's digital model: a switching MOSFET is just an effective resistance R, and the delay to move the charge on the load is:

What do you need to know — or decide — before the first line can be written? List everything the problem has to hand you.

Hint: Anything you would have to invent to get started is a thing the problem must supply.

Annotate

From (b) The digital resistor model — read this one piece at a time. What is each part doing?

On: \( t_p=0.7\,R\,C_{tot} \)

• Estimate R from the device's on-current, R ~ VDD/(2*ID,sat). The strong driver (10/1) has a small R (~0.2 kohm); the weak load (10/5) has ~5x that (the W/L ratio).
• tPHL (output falling) is set by whichever device discharges CL; tPLH (rising) by whichever charges it. Different devices, different R - so the delays differ.

Predict first

In the NMOS-load inverter the driver (10/1) is 5x stronger than the load (10/5), so:

Commit before you compute: what does (b) Why tPHL and tPLH are asymmetric come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.

Correct: Read the qualitative result

Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. tPLH >> tPHL. Lecture 11 states it directly for these configs: because R_load != R_driver, the switching times are asymmetric, with tLH > tHL.

Comparison matrix

From (b) Why tPHL and tPLH are asymmetric: refill the delay (CL=100fF) column from what you know. The rest of the table is as it appeared.

Predict first

A student writes this, and it looks reasonable:

Assuming tPHL = tPLH because 'it's an inverter.'

It is wrong. Say what breaks — and say it before you turn the page.

Correct: True only for a balanced CMOS inverter sized so Rn = Rp.

Compute each edge from the device that drives it.

Why: True only for a balanced CMOS inverter sized so Rn = Rp. These are RATIOED inverters with a deliberately weak load.

Sort into buckets

Some of these hold up and some are the exact mistakes this lesson is built to prevent. Sort them.

Holds up

In both, the load is always on and the driver is input-controlled - so the output is a tug-of-war set by the size ratio. That is ratioed logic.; At any operating point the load current = driver current. Choosing each device's region (triode vs saturation) and equating currents is the whole VTC method (Lecture 11).

Breaks

Reading the NMOS-load inverter like a CMOS inverter and writing VOH = VDD = 5 V.; Assuming tPHL = tPLH because 'it's an inverter.'

sound

These are stated as this lesson states them — each one survives the edge cases HW3 · P5: Inverter VTC & Delays (Baker 11.14) puts it through.

flawed

Each of these is lifted from a trap in this deck: reasonable-sounding, and wrong in a way that only shows up once you rely on it.

Eliminate the wrong options

The output-high voltage VOH of the NMOS-load inverter is:

3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.

• A. 4.2 V (= VDD - VTHN)
• B. 5 V (= VDD)
• C. 0.9 V (= |VTHP|)
• D. 1.85 V (= VSP)

Survives elimination: A

Why: The NMOS load shuts off when its source reaches VDD - VTHN, so it can only pull the output up to 4.2 V. The high is degraded by one NMOS threshold - the defining feature of an NMOS-load inverter (the same drop as an NMOS pass gate in P4).

Check your understanding

The output-high voltage VOH of the NMOS-load inverter is:

• A. 4.2 V (= VDD - VTHN) (correct)
• B. 5 V (= VDD)
• C. 0.9 V (= |VTHP|)
• D. 1.85 V (= VSP)

Answer: A

Why: The NMOS load shuts off when its source reaches VDD - VTHN, so it can only pull the output up to 4.2 V. The high is degraded by one NMOS threshold - the defining feature of an NMOS-load inverter (the same drop as an NMOS pass gate in P4).

Why B tempts people

That assumes a full-rail high like a complementary CMOS inverter. An NMOS load always loses one VTHN on the high side.

Why C tempts people

That is the degraded LOW of the PMOS-load inverter (its dual), not the NMOS-load high.

Why D tempts people

That is the switching point VSP, where Vin = Vout on the transition - not the output-high level.

Eliminate the wrong options

Comparing the two edges of the NMOS-load inverter:

3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.

• A. tPLH > tPHL, because the weak load charges the output high
• B. tPHL > tPLH, because the strong driver charges the output
• C. tPLH = tPHL, since both go through the same node
• D. tPHL > tPLH, because the load is weaker than the driver

Survives elimination: A

Why: The rising edge (tPLH) is driven by the always-on NMOS LOAD (10/5), which is ~5x weaker than the driver, so its effective R is ~5x larger and tPLH ~ 0.7RCtot is the larger delay. The falling edge (tPHL) uses the strong driver (10/1) and is fast. So tPLH > tPHL.

Check your understanding

Comparing the two edges of the NMOS-load inverter:

• A. tPLH > tPHL, because the weak load charges the output high (correct)
• B. tPHL > tPLH, because the strong driver charges the output
• C. tPLH = tPHL, since both go through the same node
• D. tPHL > tPLH, because the load is weaker than the driver

Answer: A

Why: The rising edge (tPLH) is driven by the always-on NMOS LOAD (10/5), which is ~5x weaker than the driver, so its effective R is ~5x larger and tPLH ~ 0.7RCtot is the larger delay. The falling edge (tPHL) uses the strong driver (10/1) and is fast. So tPLH > tPHL.

Why B tempts people

The strong driver pulls the output DOWN (tPHL), making that edge FAST, not slow. It does not set the slow rising edge.

Why C tempts people

The two edges are driven by DIFFERENT devices (driver vs load) with very different strengths, so the delays are not equal - that is the whole asymmetry.

Why D tempts people

The conclusion (load weaker than driver) is true, but a weak load makes the RISING edge slow (tPLH), not tPHL. tPHL uses the strong driver.

Draw it

One page, no notation unless you need it: draw how these connect — Part (a) NMOS-load inverter · Part (a) continued PMOS-load inverter · Part (b) Delays into 100 fF. Put an arrow wherever one of them is what makes another possible, and label the arrow with why.