HW3 · P2: Two-Stage Op-Amp (Baker Example)

Discussion prompt

Before we open HW3 · P2: Two-Stage Op-Amp (Baker Example): without looking back, what was the main idea of HW3 · P1: Differential Amplifier (Baker 22.16), and what could you do by the end of it that you could not do before?

Hint: One sentence for the idea, one for the skill. If the second one is blank, that is the part to revisit.

Comparison matrix

From Table 9.2 - the short-channel process: refill the NMOS column from what you know. The rest of the table is as it appeared.

Discussion prompt

Lecture 8's template: an op-amp chains stages with complementary jobs.

That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.

Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.

Put in order

These are the steps of Recipe: analyze any two-stage op-amp, scrambled. Put them back in order before the next slide shows you.

1. Bias: trace the reference (Fig. 20.47) to each branch current; read gm, ro from Table 9.2.
2. Stage gains: Av1 = gm1*(ro2||ro4) (simple mirror load); Av2 = gm7*ro7 (cascode sink, so its resistance drops out).
3. Open-loop gain: Av = Av1 * Av2 (gains multiply).
4. Uncompensated poles: one at node A, one at vout - dangerously close.
5. Add Cc: Miller-multiplies at node A, splitting the poles; sets fun = gm1/(2*pi*Cc).
6. Add Rz = 1/gm7: cancels the right-half-plane zero the feedforward through Cc creates.

Why: This is the order the recipe itself gives. Recalling the sequence without the slide in front of you is the difference between recognising the method and being able to run it — most of what goes wrong in practice is a step done out of turn.

Discussion prompt

Recipe: analyze any two-stage op-amp works on the cases you have just seen. Push it to the edge: what is the most degenerate input it still handles — empty, zero, one item, everything equal — and what is the first case where it stops being true? Name the case, not just "it breaks".

Hint: Try the smallest legal input, then the largest, then the one where two things collide. Methods are specified at their edges; the middle takes care of itself.

Predict first

M1's signal current is id = gm1*(vid/2). The diode-connected M3 turns it into a voltage; M4 copies that current and pushes it into node A (Lecture 8). M2 simultaneously pulls its own id from node A.

Commit before you compute: what does Stage 1 - the mirror's factor of two come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.

Correct: The two currents add

Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. M4 delivers +id and M2 delivers +id into node A, so the node sees 2(gm1vid/2) = gm1*vid.

Animation

Shows: Each line of the worked example "Stage 1 - the mirror's factor of two", appearing one at a time.

The same working the example does, in the order a tutor would write it.

Takeaway: M4 delivers +id and M2 delivers +id into node A, so the node sees 2(gm1vid/2) = gm1*vid. The mirror's 'factor of 2' makes the single-ended output carry the FULL pair transconductance with no loss of gain.

Discussion prompt

Node A is high-impedance: ro2 (from M2) in parallel with ro4 (from M4). Using Table 9.2 (ro_n = 167 k, ro_p = 333 k):

What do you need to know — or decide — before the first line can be written? List everything the problem has to hand you.

Hint: Anything you would have to invent to get started is a thing the problem must supply.

Animation

Shows: Each line of the worked example "Stage 1 - the gain Av1", appearing one at a time.

The same working the example does, in the order a tutor would write it.

Takeaway: Av1 = gm1*(ro2||ro4) = 150 uA/V * 111 kohm = 16.7. One short-channel stage gives a gain of about 17.

Predict first

A student writes this, and it looks reasonable:

Assuming the single-ended output only gets half the pair's transconductance.

It is wrong. Say what breaks — and say it before you turn the page.

Correct: True for a resistively loaded pair read single-ended - but this pair has an ACTIVE mirror, which folds the other half back in.

The current mirror adds the second half at node A.

Why: True for a resistively loaded pair read single-ended - but this pair has an ACTIVE mirror, which folds the other half back in.

Fill in the blanks

From Stage 2 - the gain Av2 — finish the line. Write what belongs on the right of the equals sign before you look.

A_g_{m7}\,r_{o7}\approx 50 = ___

Why: Producing the right-hand side unprompted is the difference between recognising this line and being able to use it. Av2 = gm7*ro7 = 150 uA/V * 333 kohm = 50 - the full intrinsic gain gm*ro of the PMOS (Table 9.2).

Animation

Shows: Each line of the worked example "Stage 2 - the gain Av2", appearing one at a time.

The same working the example does, in the order a tutor would write it.

Takeaway: A common-source stage inverts (negative gain). Stage 1 also inverts, so the op-amp's vp/vm polarities come out correct overall.

Predict first

Cascaded voltage gains multiply - the output of stage 1 is the input of stage 2:

Commit before you compute: what does Total open-loop gain come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.

Correct: Express in dB

Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. 20*log10(835) = 58 dB. Stage 1's simple-mirror load holds it to ~17, but stage 2's cascode load lets it reach the full PMOS intrinsic gain of 50 - so the product is ~835, not the ~280 you'd get treating both loads as simple devices. CONFIRM in SPICE (.ac, no load cap); the exact value depends on the Fig. 20.47 bias current.

Draw it

Translate both ways. First write the expression above as a sentence with no symbols in it at all. Then cover it, and write your sentence back as notation. If the two versions disagree, the disagreement is the thing to fix.

Predict first

A student writes this, and it looks reasonable:

Treating the cascade as if the gains add because the stages are 'in series'.

It is wrong. Say what breaks — and say it before you turn the page.

Correct: Confuses cascading with summing.

Each stage scales the previous output, so the gains multiply.

Why: Confuses cascading with summing. 17 + 50 = 67 badly under-counts the real gain.

Discussion prompt

The rule this trap just fixed:

Each stage scales the previous output, so the gains multiply.

Now break it on purpose. Build a case that violates it and follow the consequences until something visibly fails. Where does the failure first show up — and would you have noticed it if you had not been looking?

Hint: The dangerous rules are the ones whose violation still produces an answer. If yours fails loudly, try to find one that fails quietly.

Discussion prompt

Explain Why it needs compensating by analogy to something with no Analog CMOS IC Design in it at all — a queue, a recipe, a map, a bank balance, whatever fits. Then say where your analogy breaks.

Hint: An analogy that never breaks is not an analogy, it is the same idea wearing a hat. Find the seam — that is the part that is actually new.

Discussion prompt

Connect Cc from vout back to node A. Stage 2's gain Av2 makes that capacitor look huge at node A - it appears as Cc*(1+|Av2|) (the Miller effect).

That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.

Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.

Discussion prompt

With one dominant pole, the gain-bandwidth product is the input transconductance driving the Miller capacitor:

What do you need to know — or decide — before the first line can be written? List everything the problem has to hand you.

Hint: Anything you would have to invent to get started is a thing the problem must supply.

Animation

Shows: Each line of the worked example "The unity-gain (gain-bandwidth) frequency", appearing one at a time.

The same working the example does, in the order a tutor would write it.

Takeaway: gm1 = 150 uA/V. For a representative Cc = 1 pF: fun = 150 uA/V /(2pi1 pF) = 23.9 MHz. Bigger Cc = slower but more stable; Cc is the designer's stability knob.

Predict first

Cc also lets the input feed forward straight to the output, creating a right-half-plane (RHP) zero at gm7/(2*pi*Cc). A RHP zero adds phase lag - the opposite of what a normal zero does - eating your phase margin.

Commit before you compute: what does The nulling resistor Rz come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.

Correct: Choose Rz = 1/gm7

Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. Setting Rz = 1/gm7 = 1/(150 uA/V) = 6.67 kohm sends the zero to infinity (the feedforward current exactly cancels M7's forward current).

Discussion prompt

Work backwards. The example finished here:

Choose Rz = 1/gm7

What was it asked to do, and what must it have been given? Reconstruct the problem from its answer.

Hint: Every quantity in the result had to enter somewhere. Account for each one.

Predict first

A student writes this, and it looks reasonable:

Adding Cc for the dominant pole but omitting Rz.

It is wrong. Say what breaks — and say it before you turn the page.

Correct: The feedforward path through Cc leaves a RHP zero near fun.

Pair Cc with a nulling resistor Rz.

Why: The feedforward path through Cc leaves a RHP zero near fun. It adds phase lag exactly where you need margin - the op-amp rings or is only conditionally stable.

Sort into buckets

Some of these hold up and some are the exact mistakes this lesson is built to prevent. Sort them.

Holds up

Notice the intrinsic gain is small (25, 50) - that is the whole reason this op-amp needs two gain stages. A short-channel device alone cannot make enough gain.; Lecture 8's template: an op-amp chains stages with complementary jobs.; Two gain stages means two high-impedance nodes - node A and vout - each with a pole. Uncompensated, those poles sit close together.

Breaks

Assuming the single-ended output only gets half the pair's transconductance.; Treating the cascade as if the gains add because the stages are 'in series'.

sound

These are stated as this lesson states them — each one survives the edge cases HW3 · P2: Two-Stage Op-Amp (Baker Example) puts it through.

flawed

Each of these is lifted from a trap in this deck: reasonable-sounding, and wrong in a way that only shows up once you rely on it.

Comparison matrix

From Describe the operation in SPICE: refill the expect column from what you know. The rest of the table is as it appeared.

Eliminate the wrong options

The two-stage open-loop DC gain is closest to:

3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.

• A. ~835 (58 dB)
• B. ~280 (49 dB)
• C. ~67 (37 dB)
• D. ~17 (25 dB)

Survives elimination: A

Why: Cascaded gains multiply: Av = Av1Av2 = 1750 = 835, i.e. 58 dB. Stage 1's simple mirror caps it at ~17, but stage 2's cascode sink lets that stage reach the full PMOS intrinsic gain gm*ro = 50.

Check your understanding

The two-stage open-loop DC gain is closest to:

• A. ~835 (58 dB) (correct)
• B. ~280 (49 dB)
• C. ~67 (37 dB)
• D. ~17 (25 dB)

Answer: A

Why: Cascaded gains multiply: Av = Av1Av2 = 1750 = 835, i.e. 58 dB. Stage 1's simple mirror caps it at ~17, but stage 2's cascode sink lets that stage reach the full PMOS intrinsic gain gm*ro = 50.

Why B tempts people

Treats the cascode sink M8 as a SIMPLE device (ro8 = 167k), so Av2 = gm7(ro7||167k) ~ 17 and the product is 1717 = 280. The cascode makes the sink resistance >> ro7, so Av2 reaches 50, not 17.

Why C tempts people

Added the stage gains (17+50) instead of multiplying. Cascaded stages multiply because each scales the previous output.

Why D tempts people

That is a single stage. The whole reason for two stages is to multiply two of them together.

Eliminate the wrong options

The nulling resistor Rz = 1/gm7 is there to:

3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.

• A. Cancel the right-half-plane zero from the Cc feedforward path
• B. Set the dominant pole frequency
• C. Increase the DC open-loop gain
• D. Lower the output resistance of stage 2

Survives elimination: A

Why: Cc lets the input feed forward to the output, making a RHP zero at gm7/(2piCc) that subtracts phase margin. Rz = 1/gm7 pushes that zero to infinity (or into the LHP), restoring the margin.

Check your understanding

The nulling resistor Rz = 1/gm7 is there to:

• A. Cancel the right-half-plane zero from the Cc feedforward path (correct)
• B. Set the dominant pole frequency
• C. Increase the DC open-loop gain
• D. Lower the output resistance of stage 2

Answer: A

Why: Cc lets the input feed forward to the output, making a RHP zero at gm7/(2piCc) that subtracts phase margin. Rz = 1/gm7 pushes that zero to infinity (or into the LHP), restoring the margin.

Why B tempts people

The dominant pole is set by Cc and the Miller effect (p1 ~ 1/(2piRout1Av2*Cc)), not by Rz. Rz only moves the zero.

Why C tempts people

Rz does not change the DC gain - at DC the capacitor Cc is open, so the compensation branch carries no current and the gain is still Av1*Av2.

Why D tempts people

Output resistance of stage 2 is set by ro7 (the cascode sink M8 barely loads it), not by the compensation network. Rz acts on the zero, not the output impedance.

Draw it

One page, no notation unless you need it: draw how these connect — Stage 1 The active-load diff pair · Stage 2 The common-source booster · Compensation Cc and Rz. Put an arrow wherever one of them is what makes another possible, and label the arrow with why.