Part 2 of 2 for ENEE 411 Homework 2, covering the four small-signal problems. Every DC bias is set at 20 uA, so gm is 155 uA/V and ro is 833 k throughout. Problem 21.26 derives the common-gate gain, (1/gmp||rop||ron)/(1/gmn||ron), which reduces to roughly gmn/gmp and therefore to about 1. Problem 21.30 works out the cascode amplifier's three gains: vd1b/vin is about -1 because the cascode node hides the gain, vout/vd1b is about +8300, and vout/vin is about -8300, or 78 dB. Problem 21.7 finds a common-source stage's midband gain and the low-frequency high-pass corner set by the large coupling capacitor. Problem 21.36 gives a midband gain of about 128 (42 dB), a high-frequency pole near 19 kHz from the 10 pF load, an output of about 25 mV, inverted, for a 1 MHz 10 mV drive, and a unity-gain frequency fu = gm/(2*pi*CL) of about 2.47 MHz. The 38 slides include schematic, Bode, and waveform SVGs, four traps, four checks, and a SPICE-verification slide.
Subject: Analog CMOS IC Design · 76 slides · diagram-first lesson
Open the interactive version of this deck · Homework for this lesson
Title
ENEE 411 · Problems 21.7 · 21.26 · 21.30 · 21.36
Four amplifiers, one bias point. Derive the common-gate gain, split a cascode's gain across its nodes, and read frequency response straight off the poles.
Objectives
Every gain and every corner frequency here comes from the same operating point you found in Part 1: each branch sits at ~20 uA, so gm ~ 155 uA/V and ro ~ 833 k for every device. By the end you can:
Warm-up
Discussion prompt
Before we open HW2 · Small-Signal Gain & Frequency Response (Baker 21.7, 21.26, 21.30, 21.36): without looking back, what was the main idea of HW2 · DC Bias: Currents & Saturation (Baker 20.25, 20.45), and what could you do by the end of it that you could not do before?
Hint: One sentence for the idea, one for the skill. If the second one is blank, that is the part to revisit.
Answer:
ENEE 411 Homework 2, Part 1 of 2 - the two DC-operating-point problems worked end to end with the Baker long-channel process. Problem 20.25: trace VSG through a PMOS mirror to get the current in M3 (10 uA first order, ~11 uA with channel-length modulation).
Concept
Replace every saturated MOSFET by a transconductance gm (a controlled current gm*vgs) in parallel with an output resistance ro. Two formulas generate every number today:
\[ g_m=\sqrt{2\,KP\,\tfrac{W}{L}\,I_D}\qquad r_o=\frac{1}{\lambda I_D} \]
At ID = 20 uA with the long-channel table, the numbers are almost identical for N and P here (the sizes were chosen that way):
Counterexample
Discussion prompt
Replace every saturated MOSFET by a transconductance gm (a controlled current gm*vgs) in parallel with an output resistance ro. Two formulas generate every number today:
That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.
Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.
Answer:
At ID = 20 uA with the long-channel table, the numbers are almost identical for N and P here (the sizes were chosen that way):
Concept
Every voltage gain in this homework is the same product: a transconductance turns the input voltage into a current, and that current develops the output across whatever resistance sits at the output node.
\[ A_v=-\,G_m\,R_{out} \]
So the work is always: (1) find Gm (often just gm of the input device), and (2) find Rout (the hard part - it can be 1/gm, ro, or a cascode's gm*ro*ro).
Ranking
Put in order
These are the steps of Recipe: any single-stage gain or corner, scrambled. Put them back in order before the next slide shows you.
ID, then gm and ro for every device (done - all 20 uA).gm-ratio for a buffer).1/gm, ro, or cascode gm*ro^2).1/(2*pi*R*C) - coupling caps set low corners, load caps set high corners.Why: This is the order the recipe itself gives. Recalling the sequence without the slide in front of you is the difference between recognising the method and being able to run it — most of what goes wrong in practice is a step done out of turn.
Pattern
Four moves cover all four problems. Run them in order:
ID, then gm and ro for every device (done - all 20 uA).gm-ratio for a buffer).1/gm, ro, or cascode gm*ro^2).1/(2*pi*R*C) - coupling caps set low corners, load caps set high corners.Edge cases
Discussion prompt
Recipe: any single-stage gain or corner works on the cases you have just seen. Push it to the edge: what is the most degenerate input it still handles — empty, zero, one item, everything equal — and what is the first case where it stops being true? Name the case, not just "it breaks".
Hint: Try the smallest legal input, then the largest, then the one where two things collide. Methods are specified at their edges; the middle takes care of itself.
Answer:
Four moves cover all four problems. Run them in order:
Section
Problem 4 · derive the given result
Concept

M2 (NMOS, 10/2) is the amplifier. Its gate is held at a DC bias by the M1/20 uA mirror through a Big resistor and tied to AC ground by a Big cap.
The signal vin enters at M2's source; the output is at M2's drain, loaded by the diode-connected PMOS M3 (30/2), which presents 1/gmp in parallel with rop.
Bias: M2 copies M1's 20 uA, so gmn = 155 uA/V; M3 carries the same 20 uA, so gmp = 155 uA/V.
Analogy
Discussion prompt
Explain The circuit: a common-gate stage by analogy to something with no Analog CMOS IC Design in it at all — a queue, a recipe, a map, a bank balance, whatever fits. Then say where your analogy breaks.
Hint: An analogy that never breaks is not an analogy, it is the same idea wearing a hat. Find the seam — that is the part that is actually new.
Answer:
M2 (NMOS, 10/2) is the amplifier. Its gate is held at a DC bias by the M1/20 uA mirror through a Big resistor and tied to AC ground by a Big cap.
Picture it
Figure (svg): Input vin pushes into a low resistance 1 over gmn at the source; the resulting current flows up and develops vout across a larger output resistance Rout. Gain equals Rout divided by the source resistance.
Discussion prompt
Read the picture before the words. What is this showing, and what is the one thing it is built to make obvious? Commit to an answer, then read on.
Hint: Name the parts, then say what changes between them — and if nothing changes, say what is being held still.
Answer:
Drive the source, hold the gate still: the transistor passes the input as a current up to its drain, where the load turns it back into a voltage. Gain is just the ratio of two resistances.
Intuition
Drive the source, hold the gate still: the transistor passes the input as a current up to its drain, where the load turns it back into a voltage. Gain is just the ratio of two resistances.
Figure (svg): Input vin pushes into a low resistance 1 over gmn at the source; the resulting current flows up and develops vout across a larger output resistance Rout. Gain equals Rout divided by the source resistance.
Note the non-inverting sign: push current into the source and the drain voltage rises. That's the opposite of a common-source stage.
Explain it
Discussion prompt
Explain Common gate = a current buffer with a load to a student a year behind you. No notation, no jargon they have not met — and it still has to be true.
Hint: If your explanation needs a symbol they have never seen, you are describing the notation rather than the idea.
Answer:
Drive the source, hold the gate still: the transistor passes the input as a current up to its drain, where the load turns it back into a voltage. Gain is just the ratio of two resistances.
Estimation
Predict first
With the gate at AC ground, the resistance seen looking into M2's source is the device's 1/gmn in parallel with its own ron:
Commit before you compute: what does Step 1 - resistance looking into the source come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Put numbers in
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. 1/gmn = 1/155uA = 6.45 k, in parallel with ron = 833 k -> 6.40 k.
Worked example
With the gate at AC ground, the resistance seen looking into M2's source is the device's 1/gmn in parallel with its own ron:
\[ R_{in}=\frac{1}{g_{mn}}\,\|\,r_{on}\ \approx\ \frac{1}{g_{mn}} \]
Put numbers in
Why: 1/gmn = 1/155uA = 6.45 k, in parallel with ron = 833 k -> 6.40 k. The 1/gmn dominates because ron is huge.
Picture it
Animation
Shows: Each line of the worked example "Step 1 - resistance looking into the source", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: 1/gmn = 1/155uA = 6.45 k, in parallel with ron = 833 k -> 6.40 k. The 1/gmn dominates because ron is huge.
Missing information
Discussion prompt
At the drain, three things sit in parallel: the diode load 1/gmp, the load's own rop, and M2's ron looking down:
What do you need to know — or decide — before the first line can be written? List everything the problem has to hand you.
Hint: Anything you would have to invent to get started is a thing the problem must supply.
Answer:
1/gmp = 6.45 k dominates the two 833 k resistors -> Rout = 6.35 k. The diode-connected PMOS is a low-resistance load.
Worked example
At the drain, three things sit in parallel: the diode load 1/gmp, the load's own rop, and M2's ron looking down:
\[ R_{out}=\frac{1}{g_{mp}}\,\|\,r_{op}\,\|\,r_{on}\ \approx\ \frac{1}{g_{mp}} \]
Put numbers in
Why: 1/gmp = 6.45 k dominates the two 833 k resistors -> Rout = 6.35 k. The diode-connected PMOS is a low-resistance load.
Picture it
Animation
Shows: Each line of the worked example "Step 2 - resistance at the output node", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: 1/gmp = 6.45 k dominates the two 833 k resistors -> Rout = 6.35 k. The diode-connected PMOS is a low-resistance load.
Worked example
Same current flows through source and drain, so the gain is the resistance ratio - exactly the form the problem asks you to show:
\[ \frac{v_{out}}{v_{in}}=\frac{\tfrac{1}{g_{mp}}\,\|\,r_{op}\,\|\,r_{on}}{\tfrac{1}{g_{mn}}\,\|\,r_{on}} \]
Large-ro limit
Why: Drop the ro terms (they dominate the parallels): the ratio collapses to (1/gmp)/(1/gmn) = gmn/gmp.
\[ \frac{v_{out}}{v_{in}}\approx\frac{g_{mn}}{g_{mp}} \]
Number: gmn = gmp = 155 uA/V (the sizes were chosen so), so Av ~ 1.0 (0 dB). This stage is a non-inverting unity buffer - confirm with .tran and .ac.
Anomaly
Predict first
A student writes this, and it looks reasonable:
Seeing an NMOS with a PMOS load and assuming gate input, inverting gain.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: That is the common-source result.
Identify the input node first: signal enters the source, gate is AC ground -> common gate.
Why: That is the common-source result. Here the gate is AC-grounded - it is not the input - so this model is the wrong topology.
Trap
Seeing an NMOS with a PMOS load and assuming gate input, inverting gain.
Write Av = -gmn*Rout
Why: That is the common-source result. Here the gate is AC-grounded - it is not the input - so this model is the wrong topology.
Predict a large inverting gain
Why: Gives a big negative number. SPICE would show ~ +1: the source is the input and the stage does not invert.
Identify the input node first: signal enters the source, gate is AC ground -> common gate.
Write Av = Rout / Rin,source
Why: Source-driven, drain-output: gain is the resistance ratio, non-inverting.
Av ~ gmn/gmp ~ +1
Why: Matches the given formula and the SPICE result. The PMOS being diode-connected (1/gmp load) is what makes the gain ~1.
Elimination
Eliminate the wrong options
In the large-ro limit, vout/vin is closest to:
3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.
Survives elimination: A
Why: Common-gate gain is Rout/Rin,source = (1/gmp||rop||ron)/(1/gmn||ron) ~ gmn/gmp. With gmn = gmp here, that is ~ +1, and it is non-inverting because the input is at the source.
Check
M2 is common-gate (NMOS, gmn), loaded by diode-connected M3 (PMOS, gmp). Here gmn = gmp = 155 uA/V.
Check your understanding
In the large-ro limit, vout/vin is closest to:
Answer: A
Why: Common-gate gain is Rout/Rin,source = (1/gmp||rop||ron)/(1/gmn||ron) ~ gmn/gmp. With gmn = gmp here, that is ~ +1, and it is non-inverting because the input is at the source.
Section
Problem 5 · where the gain lives
Concept

vin drives M1B (common source). Its drain is the inner node vd1b, which feeds the source of the cascode device M1T (gate AC-grounded). M1T's drain is vout.
The load is a cascode PMOS current source (M2T over M2B). Per the hint, replace it by its output resistance Rocasp - a cascode multiplies ro by ~gm*ro.
All devices at 20 uA: gm = 155 uA/V, ro = 833 k. We want three gains: vout/vin, vd1b/vin, vout/vd1b.
Picture it
Figure (svg): Bar chart of gain magnitude: from vin to vd1b the gain is about 1, but from vd1b to vout it is about 8300, so vin to vout is about 8300.
Discussion prompt
Read the picture before the words. What is this showing, and what is the one thing it is built to make obvious? Commit to an answer, then read on.
Hint: Name the parts, then say what changes between them — and if nothing changes, say what is being held still.
Answer:
The cascode device M1T pins its source (vd1b) almost still - looking into a source is a low 1/gm. So the inner node barely swings: the input stage works into ~1/gm1T and gets only ~unity gain there.
Intuition
The cascode device M1T pins its source (vd1b) almost still - looking into a source is a low 1/gm. So the inner node barely swings: the input stage works into ~1/gm1T and gets only ~unity gain there.
Figure (svg): Bar chart of gain magnitude: from vin to vd1b the gain is about 1, but from vd1b to vout it is about 8300, so vin to vout is about 8300.
All the gain reappears at vout, because the cascode raises Rout enormously (Rocasn || Rocasp). The current is the same everywhere; only the resistance it lands on changes.
Estimation
Predict first
M1B is a common-source device whose load is the resistance looking into M1T's source, ~1/gm1T. So:
Commit before you compute: what does Gain 1 - vd1b/vin (the inner node) come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Both 10/2 at 20 uA
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. gm1B = gm1T = 155 uA/V, so the ratio is -1.
Worked example
M1B is a common-source device whose load is the resistance looking into M1T's source, ~1/gm1T. So:
\[ \frac{v_{d1b}}{v_{in}}\approx -g_{m1B}\cdot\frac{1}{g_{m1T}}=-\frac{g_{m1B}}{g_{m1T}} \]
Both 10/2 at 20 uA
Why: gm1B = gm1T = 155 uA/V, so the ratio is -1. The inner node mirrors the input, inverted, with ~unity magnitude.
\[ \frac{v_{d1b}}{v_{in}}\approx -1 \]
Picture it
Animation
Shows: Each line of the worked example "Gain 1 - vd1b/vin (the inner node)", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: gm1B = gm1T = 155 uA/V, so the ratio is -1. The inner node mirrors the input, inverted, with ~unity magnitude.
Fill the middle
Fill in the blanks
From Gain 2 - vout/vd1b (the cascode device) — finish the line. Write what belongs on the right of the equals sign before you look.
R_R_{ocasn}\,\|\,R_{ocasp},\quad R_{ocas}\approx g_m r_o^2 = ___
Why: Producing the right-hand side unprompted is the difference between recognising this line and being able to use it. Rocas ~ 155uA x (833k)^2 ~ 108 Mohm each; in parallel Rout ~ 53.8 Mohm.
Worked example
From the inner node up, M1T is a common-source-like stage driving the full output resistance. Its gain is gm1T*Rout, where Rout is the two cascodes in parallel:
\[ R_{out}=R_{ocasn}\,\|\,R_{ocasp},\quad R_{ocas}\approx g_m r_o^2 \]
Numbers
Why: Rocas ~ 155uA x (833k)^2 ~ 108 Mohm each; in parallel Rout ~ 53.8 Mohm.
\[ \frac{v_{out}}{v_{d1b}}\approx g_{m1T}R_{out}=155\mu\times 53.8\text{M}\approx +8300 \]
Picture it
Animation
Shows: Each line of the worked example "Gain 2 - vout/vd1b (the cascode device)", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: Rocas ~ 155uA x (833k)^2 ~ 108 Mohm each; in parallel Rout ~ 53.8 Mohm.
Worked example
The overall gain is the two stages multiplied - or directly, the input gm working into the full cascoded output resistance:
\[ \frac{v_{out}}{v_{in}}=\frac{v_{d1b}}{v_{in}}\cdot\frac{v_{out}}{v_{d1b}}\approx(-1)(8300)=-g_{m1B}R_{out} \]
Evaluate
Why: -155uA x 53.8M ~ -8300 V/V, about 78 dB. Inverting, as a common-source input should be.
\[ \frac{v_{out}}{v_{in}}\approx -8300\ \ (\approx 78\text{ dB}) \]
Magnitudes scale with ro^2, so they're sensitive to lambda - quote the form -gm*Rout and plug your section's lambda. The shape (inner ~1, output huge) is exact.
Translation
\( \frac{v_{out}}{v_{in}}\approx -8300\ \ (\approx 78\text{ dB}) \)
Draw it
Translate both ways. First write the expression above as a sentence with no symbols in it at all. Then cover it, and write your sentence back as notation. If the two versions disagree, the disagreement is the thing to fix.
Anomaly
Predict first
A student writes this, and it looks reasonable:
Treating the output node like a simple stage with Rout = ro.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: Uses a single ro. That ignores the whole point of cascoding both the device and the load.
Cascoding multiplies output resistance by ~gm*ro.
Why: Uses a single ro. That ignores the whole point of cascoding both the device and the load.
Trap
Treating the output node like a simple stage with Rout = ro.
Av = -gm1B*(ron||rop)
Why: Uses a single ro. That ignores the whole point of cascoding both the device and the load.
Get ~ -129 (42 dB)
Why: Off by ~gm*ro (~65x). You'd report a plain intrinsic-gain stage and miss two orders of magnitude.
Cascoding multiplies output resistance by ~gm*ro.
Rout = Rocasn||Rocasp, Rocas ~ gm*ro^2
Why: Both the NMOS cascode and the PMOS cascode load present ~108 Mohm; in parallel ~53.8 Mohm.
Av = -gm1B*Rout ~ -8300 (78 dB)
Why: The cascode buys ~36 dB over the single-stage value. That is why you cascode.
Break the constraint
Discussion prompt
The rule this trap just fixed:
Both the NMOS cascode and the PMOS cascode load present ~108 Mohm; in parallel ~53.8 Mohm.
Now break it on purpose. Build a case that violates it and follow the consequences until something visibly fails. Where does the failure first show up — and would you have noticed it if you had not been looking?
Hint: The dangerous rules are the ones whose violation still produces an answer. If yours fails loudly, try to find one that fails quietly.
Answer:
Uses a single ro. That ignores the whole point of cascoding both the device and the load.
Check
In the cascode, gm1B = gm1T = 155 uA/V and the cascoded Rout ~ 53.8 Mohm.
Check your understanding
Which statement matches the three gains?
Answer: A
Why: The inner node is loaded by 1/gm1T (looking into the cascode source), so vd1b/vin ~ -gm1B/gm1T ~ -1. The cascode device then drives the full Rout, giving vout/vd1b ~ gm1T*Rout ~ +8300. Their product is vout/vin ~ -8300.
Section
Problem 3 · the low-frequency corner
Concept

M2 (PMOS) is the common-source amplifier; its gate is the input. M1 (NMOS, biased by Vbias4) is a current-source load, so the output node sees ro2 || ro1.
The input arrives through 100k and a Big coupling cap. Use the long-channel sizes/biasing from Table 9.1 for the device values.
We want the frequency response: midband gain plus where it rolls off.
Explain it
Discussion prompt
Explain The circuit: common-source with coupling to a student a year behind you. No notation, no jargon they have not met — and it still has to be true.
Hint: If your explanation needs a symbol they have never seen, you are describing the notation rather than the idea.
Answer:
M2 (PMOS) is the common-source amplifier; its gate is the input. M1 (NMOS, biased by Vbias4) is a current-source load, so the output node sees ro2 || ro1.
Intuition
A series ('coupling') cap is an open at DC and a short at high frequency. So it kills the response at low frequencies and lets the midband through - this is a high-pass edge, not a high-frequency roll-off.
Because the cap is Big, its corner sits at a very low frequency. Across the audio/midband, treat it as a short and the gain is flat.
Analogy
Discussion prompt
Explain A coupling cap blocks DC, passes signal by analogy to something with no Analog CMOS IC Design in it at all — a queue, a recipe, a map, a bank balance, whatever fits. Then say where your analogy breaks.
Hint: An analogy that never breaks is not an analogy, it is the same idea wearing a hat. Find the seam — that is the part that is actually new.
Answer:
Because the cap is Big, its corner sits at a very low frequency. Across the audio/midband, treat it as a short and the gain is flat.
Fill the middle
Fill in the blanks
From Midband gain — finish the line. Write what belongs on the right of the equals sign before you look.
A_-g_{m2}\,(r_{o2}\,\|\,r_{o1}) = ___
Why: Producing the right-hand side unprompted is the difference between recognising this line and being able to use it. With gm ~ 155 uA/V and ro ~ 833 k (ID = 20 uA), ro2||ro1 ~ 417 k gives |Av| ~ gm*ro/2 ~ 64 (~36 dB).
Worked example
With the coupling cap shorted, M2 is a textbook common-source stage into the current-source load:
\[ A_{v,mid}=-g_{m2}\,(r_{o2}\,\|\,r_{o1}) \]
Plug Table 9.1 values
Why: With gm ~ 155 uA/V and ro ~ 833 k (ID = 20 uA), ro2||ro1 ~ 417 k gives |Av| ~ gm*ro/2 ~ 64 (~36 dB). Use your section's exact sizes/bias from the table.
Picture it
Animation
Shows: Each line of the worked example "Midband gain", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: With gm ~ 155 uA/V and ro ~ 833 k (ID = 20 uA), ro2||ro1 ~ 417 k gives |Av| ~ gm*ro/2 ~ 64 (~36 dB). Use your section's exact sizes/bias from the table.
Worked example
Figure (svg): Bode magnitude plot: gain rises at plus 20 dB per decade at low frequency, then flattens at the midband gain above the corner frequency fL set by the coupling capacitor. It is a high-pass shape.
The series 100k and the gate node charge through the Big cap, making one low-frequency pole:
\[ f_L=\frac{1}{2\pi R\,C_{big}} \]
Interpret
Why: Below fL the coupling cap blocks signal (gain climbs at +20 dB/dec); above fL it is a short and the gain is flat at Av,mid. 'Big' C => fL is very low.
So the response is high-pass into flat: rising skirt, a knee at fL, then the midband plateau. (Device caps eventually add a high-frequency pole far above midband.)
Anomaly
Predict first
A student writes this, and it looks reasonable:
Seeing a capacitor and assuming the gain falls at high frequency.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: Confuses a series coupling cap with a shunt load cap.
Ask: is the cap in series (coupling) or to ground (load)?
Why: Confuses a series coupling cap with a shunt load cap. A series cap's impedance falls with frequency - it helps the signal through, not blocks it.
Trap
Seeing a capacitor and assuming the gain falls at high frequency.
Place a high-frequency pole at 1/(2piR*Cbig)
Why: Confuses a series coupling cap with a shunt load cap. A series cap's impedance falls with frequency - it helps the signal through, not blocks it.
Sketch a low-pass roll-off
Why: Wrong direction entirely: the Big cap sets the LOW corner. You'd predict attenuation exactly where the amp works best.
Ask: is the cap in series (coupling) or to ground (load)?
Series cap -> high-pass -> LOW corner fL
Why: Open at DC, short at high f. It blocks low frequencies and passes the midband.
Big C -> fL very low, flat midband above it
Why: The roll-off you'd draw at the top comes only from the device's own capacitances, far above fL.
Check
The input reaches M2's gate through 100k in series with a Big coupling capacitor.
Check your understanding
The Big coupling cap sets:
Answer: A
Why: A series coupling cap is open at DC and a short at high frequency, so it forms a high-pass edge with the series resistance: fL = 1/(2piR*Cbig). Above fL the gain is flat at the midband value. 'Big' makes fL very low.
Section
Problem 6 · the high-frequency corner
Concept

M2 (PMOS, 30/2) is the common-source stage. Its drain (vout) is loaded by a cascode NMOS current source (huge Rocasn) and a 10 pF capacitor to ground.
Because the cascode load's resistance is ~108 Mohm, the output resistance is set by M2's own ro2 ~ 833 k. The 10 pF sits at this node - a classic load cap, so a high-frequency pole.
Deliverables: (a) the Bode plot, (b) waveforms for 10 mV at 1 MHz, (c) the unity-gain frequency.
Counterexample
Discussion prompt
M2 (PMOS, 30/2) is the common-source stage. Its drain (vout) is loaded by a cascode NMOS current source (huge Rocasn) and a 10 pF capacitor to ground.
That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.
Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.
Answer:
Because the cascode load's resistance is ~108 Mohm, the output resistance is set by M2's own ro2 ~ 833 k. The 10 pF sits at this node - a classic load cap, so a high-frequency pole.
Fill the middle
Fill in the blanks
From Midband gain — finish the line. Write what belongs on the right of the equals sign before you look.
|A_g_{m2}\,R_{out}\approx g_{m2}\,r_{o2}| = ___
Why: Producing the right-hand side unprompted is the difference between recognising this line and being able to use it. 155 uA/V x 833 k ~ 128, about 42 dB.
Worked example
Standard common-source into the output resistance (ro2, since the cascode load is much larger):
\[ |A_{v,mid}|=g_{m2}\,R_{out}\approx g_{m2}\,r_{o2} \]
Numbers
Why: 155 uA/V x 833 k ~ 128, about 42 dB. This is just the intrinsic gain because the cascode load doesn't limit Rout.
Worked example
Figure (svg): Bode magnitude plot: flat at 42 dB up to the corner fH around 19 kHz, then falling at minus 20 dB per decade, crossing 0 dB (unity gain) at fu around 2.47 MHz.
The 10 pF load with the output resistance makes one high-frequency pole:
\[ f_H=\frac{1}{2\pi R_{out}C_L}=\frac{1}{2\pi(833\text{k})(10\text{pF})}\approx 19\ \text{kHz} \]
Bode shape
Why: Flat at |Av| = 42 dB up to fH ~ 19 kHz, then a single-pole -20 dB/decade roll-off above it. (The Big input cap's low corner is far below and ignored.)
Picture it
Animation
Shows: Each line of the worked example "(a) The high-frequency pole and Bode plot", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: Flat at |Av| = 42 dB up to fH ~ 19 kHz, then a single-pole -20 dB/decade roll-off above it. (The Big input cap's low corner is far below and ignored.)
Missing information
Discussion prompt
1 MHz is far above fH ~ 19 kHz, so we're on the -20 dB/dec slope, not the flat midband. The gain there is well below 128:
What do you need to know — or decide — before the first line can be written? List everything the problem has to hand you.
Hint: Anything you would have to invent to get started is a thing the problem must supply.
Answer:
~2.5 x 10 mV ~ 25 mV peak - barely larger than the input, because we're past the pole.
Worked example
Figure (svg): Two sine waves. The input is a small 10 mV sine. The output is a larger but only modest 25 mV sine, inverted and phase-shifted because 1 MHz is far above the 19 kHz pole.
1 MHz is far above fH ~ 19 kHz, so we're on the -20 dB/dec slope, not the flat midband. The gain there is well below 128:
\[ |A_v(1\text{MHz})|\approx|A_{v,mid}|\frac{f_H}{f}=128\cdot\frac{19\text{k}}{1\text{M}}\approx 2.5 \]
Output amplitude
Why: ~2.5 x 10 mV ~ 25 mV peak - barely larger than the input, because we're past the pole.
Phase
Why: Common source inverts (180 deg); a pole well past its corner adds another ~90 deg lag. Sketch the output ~25 mV, inverted and phase-shifted relative to the 10 mV input.
Picture it
Animation
Shows: Each line of the worked example "(b) Waveforms at 1 MHz, 10 mV", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: Common source inverts (180 deg); a pole well past its corner adds another ~90 deg lag. Sketch the output ~25 mV, inverted and phase-shifted relative to the 10 mV input.
Estimation
Predict first
For a single-pole response, the unity-gain frequency is the gain-bandwidth product: midband gain times the corner.
Commit before you compute: what does (c) Unity-gain frequency come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Notice ro cancels
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. fu depends only on gm2 and CL - not on ro or lambda.
Worked example
For a single-pole response, the unity-gain frequency is the gain-bandwidth product: midband gain times the corner.
\[ f_u=|A_{v,mid}|\cdot f_H=g_{m2}r_{o2}\cdot\frac{1}{2\pi r_{o2}C_L}=\frac{g_{m2}}{2\pi C_L} \]
Notice ro cancels
Why: fu depends only on gm2 and CL - not on ro or lambda. That makes it the robust number to quote.
\[ f_u=\frac{155\,\mu A/V}{2\pi(10\text{pF})}\approx 2.47\ \text{MHz} \]
Consistency check: at 1 MHz (below fu) the gain was ~2.5 > 1, and it reaches 1 only at ~2.47 MHz. The two answers agree.
Picture it
Animation
Shows: Each line of the worked example "(c) Unity-gain frequency", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: fu depends only on gm2 and CL - not on ro or lambda. That makes it the robust number to quote.
Anomaly
Predict first
A student writes this, and it looks reasonable:
Reporting the corner fH as the unity-gain frequency.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: At fH the gain is still |Av,mid|/sqrt(2) ~ 90, nowhere near 1.
Unity gain is where |Av| falls to 1, a factor |Av,mid| past the corner.
Why: At fH the gain is still |Av,mid|/sqrt(2) ~ 90, nowhere near 1. The corner is where roll-off starts, not where gain hits unity.
Trap
Reporting the corner fH as the unity-gain frequency.
Quote fu = fH ~ 19 kHz
Why: At fH the gain is still |Av,mid|/sqrt(2) ~ 90, nowhere near 1. The corner is where roll-off starts, not where gain hits unity.
Underestimate bandwidth ~130x
Why: Misses the whole -20 dB/dec span between fH and fu.
Unity gain is where |Av| falls to 1, a factor |Av,mid| past the corner.
fu = |Av,mid| x fH = gm/(2piCL)
Why: Walk down the -20 dB/dec slope from 42 dB to 0 dB: that is |Av,mid| in magnitude, or one factor of gain in frequency.
fu ~ 2.47 MHz
Why: ~128 x 19 kHz. And because ro cancels, this number is independent of lambda - the safe one to report.
Two truths and a lie
Sort into buckets
Some of these hold up and some are the exact mistakes this lesson is built to prevent. Sort them.
gm (a controlled current gm*vgs) in parallel with an output resistance ro. Two formulas generate every number today:; M2 (NMOS, 10/2) is the amplifier. Its gate is held at a DC bias by the M1/20 uA mirror through a Big resistor and tied to AC ground by a Big cap.; Note the non-inverting sign: push current into the source and the drain voltage rises. That's the opposite of a common-source stage.Rout = ro.Elimination
Eliminate the wrong options
The unity-gain frequency fu is closest to:
3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.
Survives elimination: A
Why: fu = |Av,mid|fH = gm2/(2piCL) = 155uA / (2pi*10pF) ~ 2.47 MHz. The ro cancels, so fu depends only on gm and CL.
Check
gm2 = 155 uA/V, CL = 10 pF, |Av,mid| ~ 128, fH ~ 19 kHz.
Check your understanding
The unity-gain frequency fu is closest to:
Answer: A
Why: fu = |Av,mid|fH = gm2/(2piCL) = 155uA / (2pi*10pF) ~ 2.47 MHz. The ro cancels, so fu depends only on gm and CL.
Concept
Problems 21.26 and 21.36 ask for SPICE confirmation. Here's what each run should reproduce - if your simulation disagrees, your hand operating point is usually the culprit.
| run | set up | expect |
|---|---|---|
| .op | DC operating point | each branch ~ 20 uA; gm, ro print ~ values used here |
| .ac | 1 Hz -> 100 MHz, AC=1 | 21.26: flat ~0 dB; 21.36: 42 dB flat, fH ~19 kHz, fu ~2.47 MHz |
| .tran | 1 MHz sine, 10 mV | 21.36: out ~25 mV, inverted; 21.26: out ~ in (gain ~1) |
Read gm and ro straight from the .op listing and recompute - that closes the loop between the hand analysis and the simulator.
Comparison
Comparison matrix
From Verifying in SPICE (.tran and .ac): refill the set up column from what you know. The rest of the table is as it appeared.
| run | set up | expect |
|---|---|---|
| .op | DC operating point | each branch ~ 20 uA; gm, ro print ~ values used here |
| .ac | 1 Hz -> 100 MHz, AC=1 | 21.26: flat ~0 dB; 21.36: 42 dB flat, fH ~19 kHz, fu ~2.47 MHz |
| .tran | 1 MHz sine, 10 mV | 21.36: out ~25 mV, inverted; 21.26: out ~ in (gain ~1) |
Connect it up
Draw it
One page, no notation unless you need it: draw how these connect — Problem 21.26 Common-Gate Gain · Problem 21.30 A Cascode's Three Gains · Problem 21.7 Frequency Response of a CS stage · Problem 21.36 Bode, Waveforms & GBW. Put an arrow wherever one of them is what makes another possible, and label the arrow with why.
Recap
| problem | key result |
|---|---|
| 21.26 common-gate | Av ~ gmn/gmp ~ 1 (0 dB) |
| 21.30 cascode | vd1b/vin ~ -1, vout/vin ~ -8300 |
| 21.7 CS response | Av,mid = -gm(ro2||ro1); fL = 1/(2piR*Cbig) |
| 21.36 Bode | fH ~19 kHz, out(1MHz) ~25 mV, fu ~2.47 MHz |
Every number traces back to one operating point (20 uA -> gm ~155 uA/V, ro ~833 k). Lock the bias, and the gains and corners follow. Confirm the two SPICE-required parts and you've got the full set.
Want this taught 1-on-1? Alexander tutors Analog CMOS IC Design — $55/session, free consultation.