ENEE 411 Homework 3, Problem 4 (Baker 10.14), rebuilt in full course notation on long-channel Table 9.1 and Lecture 10, the MOSFET pass gate. Two rules drive everything: an NMOS pass gate passes a good 0 but loses a threshold on a 1, stopping at VDD - VTHN = 4.2 V, while a PMOS pass gate passes a good 1 but loses a drop on a 0, stopping at |VTHP| = 0.9 V. Pass gates in series stack their drops, giving VDD - 2VTHN, and an NMOS high is limited by its gate rather than its drain, which is why circuit (g) still stops at 4.2 V even with 3*VDD on the drain. Circuits (a), (b), and (g) are transmission gates with both gates at VDD, so only the NMOS conducts. The deck closes with a results table for (a) through (g) - 4.2, 0, 0, 4.2, 0.9, 5, and 4.2 V - and a SPICE .op verification. Its 19 slides include pass-gate threshold-drop figures, three traps, and two checks.
Subject: Analog CMOS IC Design · 40 slides · diagram-first lesson
A single transistor passes a rail to node A. Sometimes A reaches the full rail; sometimes it stops one threshold short. Two pass-gate rules decide which - the heart of pass-transistor logic.
2. What you will be able to do
Objectives
Pure pass-gate reasoning - no square-law arithmetic. From Lecture 10. By the end you can:
State the NMOS pass-gate rule: good at passing a 0, bad at a 1 - a 1 comes through one threshold low, at VDD - VTHN.
State the PMOS pass-gate rule: good at a 1, bad at a 0 - a 0 stops at |VTHP|.
Stack drops through series pass gates (VDD - 2*VTHN) and recognize a diode clamp.
Find the voltage at A for each of circuits (a)-(g) and confirm it with a SPICE .op.
3. What survived from HW3 · P3: Three-Stage Op-Amp (Baker 24.24)?
Warm-up
Discussion prompt
Before we open HW3 · P4: Voltage at Point A (Baker 10.14): without looking back, what was the main idea of HW3 · P3: Three-Stage Op-Amp (Baker 24.24), and what could you do by the end of it that you could not do before?
Hint: One sentence for the idea, one for the skill. If the second one is blank, that is the part to revisit.
Answer:
ENEE 411 Homework 3, Problem 3 (Baker 24.24), short-channel Table 9.2 (VDD=1V, 50nm), full course-notation rebuild. Three cascaded gain stages (nested-Miller compensated, Cc1=240f + Cc2).
4. The two levels that matter
Concept
Long-channel Table 9.1. Only two numbers drive every answer here:
quantity
value
meaning
VDD
5 V
the full high rail
VTHN
0.8 V
NMOS threshold
|VTHP|
0.9 V
PMOS threshold
VDD - VTHN
4.2 V
the degraded (weak) high
|VTHP|
0.9 V
the degraded (weak) low
Body effect nudges the degraded NMOS high a little below 4.2 V (VTHN rises as the source rises). Note it, then let SPICE give the exact value.
5. Fill in: value for The two levels that matter
Comparison
Comparison matrix
From The two levels that matter: refill the value column from what you know. The rest of the table is as it appeared.
quantity
value
meaning
VDD
5 V
the full high rail
VTHN
0.8 V
NMOS threshold
|VTHP|
0.9 V
PMOS threshold
VDD - VTHN
4.2 V
the degraded (weak) high
|VTHP|
0.9 V
the degraded (weak) low
6. The MOSFET as a pass gate
Concept
Lecture 10: a MOSFET used to pass a logic level from input to output is a pass gate (PG). An NMOS PG is enabled when its gate is at VDD; a PMOS PG when its gate is at ground.
The catch: the transistor is only strong in one direction. The other direction loses one threshold. That asymmetry is the entire problem.
7. Break it if you can: The MOSFET as a pass gate
Counterexample
Discussion prompt
Lecture 10: a MOSFET used to pass a logic level from input to output is a pass gate (PG). An NMOS PG is enabled when its gate is at VDD; a PMOS PG when its gate is at ground.
That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.
Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.
Answer:
The catch: the transistor is only strong in one direction. The other direction loses one threshold. That asymmetry is the entire problem.
8. Why a pass gate 'gives up' one threshold
Intuition
Figure (svg): An NMOS pass gate with gate at VDD and drain at VDD, charging node A upward. As A rises, the gate-to-source voltage VGS = VDD minus A shrinks. When A reaches VDD minus VTHN, VGS equals VTHN and the transistor shuts off, leaving A stuck one threshold below VDD. A small graph shows A rising and flattening at VDD minus VTHN.
The rising source eats the gate drive until the device shuts off.
Drive an NMOS PG gate to VDD and let it charge A up from its drain. The NMOS conducts only while VGS > VTHN.
But as A rises, the source rises, so VGS = VDD - Ashrinks. The instant A = VDD - VTHN, VGS = VTHN and the device turns itself off. A can climb no higher. That is the degraded high - 'an NMOS is bad at passing a 1.'
Flipped for the PMOS: pulling A down stops at A = |VTHP|, because below that its VSG falls under |VTHP| and it shuts off. 'A PMOS is bad at passing a 0.'
9. Break it if you can: Why a pass gate 'gives up' one threshold
Counterexample
Discussion prompt
Drive an NMOS PG gate to VDD and let it charge A up from its drain. The NMOS conducts only while VGS > VTHN.
That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.
Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.
10. Rebuild the recipe: The pass-gate rulebook for point A
Ranking
Put in order
These are the steps of The pass-gate rulebook for point A, scrambled. Put them back in order before the next slide shows you.
Is the PG on? NMOS needs gate high; PMOS needs gate low. If off, A floats (Hi-Z).
Which rail is it passing to A? High (VDD) or low (GND).
NMOS: passing low -> A = 0 (good 0). Passing high -> A = VDD - VTHN (one drop).
PMOS: passing high -> A = VDD (good 1). Passing low -> A = |VTHP| (one drop).
Series PGs stack drops, and an NMOS high is gate-limited to Vgate - VTHN, no matter how high the drain rail is.
Why: This is the order the recipe itself gives. Recalling the sequence without the slide in front of you is the difference between recognising the method and being able to run it — most of what goes wrong in practice is a step done out of turn.
11. The pass-gate rulebook for point A
Pattern
Is the PG on? NMOS needs gate high; PMOS needs gate low. If off, A floats (Hi-Z).
Which rail is it passing to A? High (VDD) or low (GND).
NMOS: passing low -> A = 0 (good 0). Passing high -> A = VDD - VTHN (one drop).
PMOS: passing high -> A = VDD (good 1). Passing low -> A = |VTHP| (one drop).
Series PGs stack drops, and an NMOS high is gate-limited to Vgate - VTHN, no matter how high the drain rail is.
12. Where does it stop working: The pass-gate rulebook for point A
Edge cases
Discussion prompt
The pass-gate rulebook for point A works on the cases you have just seen. Push it to the edge: what is the most degenerate input it still handles — empty, zero, one item, everything equal — and what is the first case where it stops being true? Name the case, not just "it breaks".
Hint: Try the smallest legal input, then the largest, then the one where two things collide. Methods are specified at their edges; the middle takes care of itself.
Answer:
Is the PG on? NMOS needs gate high; PMOS needs gate low. If off, A floats (Hi-Z).
Which rail is it passing to A? High (VDD) or low (GND).
NMOS: passing low -> A = 0 (good 0). Passing high -> A = VDD - VTHN (one drop).
PMOS: passing high -> A = VDD (good 1). Passing low -> A = |VTHP| (one drop).
Series PGs stack drops, and an NMOS high is gate-limited to Vgate - VTHN, no matter how high the drain rail is.
13. The clear cases Good vs bad direction
Section
circuits (e) and (f)
14. Guess the shape of the answer: PMOS passing VDD - a good 1 (f)
Estimation
Predict first
Circuit (f): a PMOS PG with its gate grounded (enabled), source at VDD, passing toward A:
Commit before you compute: what does PMOS passing VDD - a good 1 (f) come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Pass the high all the way
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. A PMOS pulls its drain to its source with NO threshold drop on the high side - as A nears VDD it is still strongly on (VSG stays large).
15. PMOS passing VDD - a good 1 (f)
Worked example
Circuit (f): a PMOS PG with its gate grounded (enabled), source at VDD, passing toward A:
\[ V_{SG}=V_{DD}-0=5\,\text{V}\;>\;|V_{THP}| \]
Pass the high all the way
Why: A PMOS pulls its drain to its source with NO threshold drop on the high side - as A nears VDD it is still strongly on (VSG stays large).
\[ \boxed{V_A=V_{DD}=5\,\text{V}} \]
16. PMOS passing VDD - a good 1 (f) — line by line
Picture it
Animation
Shows: Each line of the worked example "PMOS passing VDD - a good 1 (f)", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: A PMOS pulls its drain to its source with NO threshold drop on the high side - as A nears VDD it is still strongly on (VSG stays large).
17. What has to be given first: PMOS passing GND - a bad 0 (e)
Missing information
Discussion prompt
Circuit (e): a PMOS PG (gate grounded) passing the low side toward A - the wrong direction for a PMOS.
What do you need to know — or decide — before the first line can be written? List everything the problem has to hand you.
Hint: Anything you would have to invent to get started is a thing the problem must supply.
Answer:
As A falls, the PMOS source is A and VSG = A - 0. When A reaches |VTHP|, VSG = |VTHP| and the device turns off - it cannot pull A any lower.
18. PMOS passing GND - a bad 0 (e)
Worked example
Circuit (e): a PMOS PG (gate grounded) passing the low side toward A - the wrong direction for a PMOS.
Watch it shut off on the way down
Why: As A falls, the PMOS source is A and VSG = A - 0. When A reaches |VTHP|, VSG = |VTHP| and the device turns off - it cannot pull A any lower.
\[ \boxed{V_A=|V_{THP}|=0.9\,\text{V}} \]
19. Work backwards from the answer: PMOS passing GND - a bad 0 (e)
Reverse engineer
Discussion prompt
Work backwards. The example finished here:
Watch it shut off on the way down
What was it asked to do, and what must it have been given? Reconstruct the problem from its answer.
Hint: Every quantity in the result had to enter somewhere. Account for each one.
Answer:
Circuit (e): a PMOS PG (gate grounded) passing the low side toward A - the wrong direction for a PMOS.
20. Something is wrong here: assuming A always reaches the rail
Anomaly
Predict first
A student writes this, and it looks reasonable:
Reasoning 'the transistor connects A to VDD, so A = 5 V' for an NMOS PG passing a high.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: Ignores the threshold drop. An NMOS shuts off one VTHN below its gate - it never delivers the full rail on the high side.
Match the device to the direction it is passing.
Why: Ignores the threshold drop. An NMOS shuts off one VTHN below its gate - it never delivers the full rail on the high side.
21. Trap: assuming A always reaches the rail
Trap
The trap
Reasoning 'the transistor connects A to VDD, so A = 5 V' for an NMOS PG passing a high.
Report VA = VDD = 5 V
Why: Ignores the threshold drop. An NMOS shuts off one VTHN below its gate - it never delivers the full rail on the high side.
The fix
Match the device to the direction it is passing.
NMOS passing high -> VA = VDD - VTHN = 4.2 V
Why: Strong only in its good direction (NMOS->0, PMOS->1). In the bad direction it loses one threshold. Always check polarity vs direction.
22. Break it on purpose: assuming A always reaches the rail
Break the constraint
Discussion prompt
The rule this trap just fixed:
Strong only in its good direction (NMOS->0, PMOS->1). In the bad direction it loses one threshold. Always check polarity vs direction.
Now break it on purpose. Build a case that violates it and follow the consequences until something visibly fails. Where does the failure first show up — and would you have noticed it if you had not been looking?
Hint: The dangerous rules are the ones whose violation still produces an answer. If yours fails loudly, try to find one that fails quietly.
Answer:
Ignores the threshold drop. An NMOS shuts off one VTHN below its gate - it never delivers the full rail on the high side.
23. Diode clamp, series drops & the gate limit
Section
circuit (g)
24. Guess the shape of the answer: Series pass gates stack the drops
Estimation
Predict first
Lecture 10's worked example. One NMOS PG passing a high gives VDD - VTHN. Now feed that into a second NMOS PG whose gate is also at VDD:
Commit before you compute: what does Series pass gates stack the drops come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: But if VDD-VTHN drives the GATE of the next device
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. Then that device's own output is one more VTHN below its gate: VDD - 2*VTHN.
25. Series pass gates stack the drops
Worked example
Lecture 10's worked example. One NMOS PG passing a high gives VDD - VTHN. Now feed that into a second NMOS PG whose gate is also at VDD:
First PG
Why: Output of M1 = VDD - VTHN. If the next PG's GATE is at VDD and this VDD-VTHN is its INPUT (drain), it passes through with no extra drop -> still VDD - VTHN. We only take one hit.
But if VDD-VTHN drives the GATE of the next device
Why: Then that device's own output is one more VTHN below its gate: VDD - 2*VTHN. Each threshold-limited stage in series subtracts another VTHN.
\[ V_{out}=V_{DD}-2V_{THN}=5-1.6=3.4\,\text{V} \]
26. Series pass gates stack the drops — line by line
Picture it
Animation
Shows: Each line of the worked example "Series pass gates stack the drops", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: Then that device's own output is one more VTHN below its gate: VDD - 2*VTHN. Each threshold-limited stage in series subtracts another VTHN.
27. Guess the shape of the answer: Diode clamp & the gate limit (g)
Estimation
Predict first
A diode-connected MOSFET (gate tied to drain) holds its terminal exactly one threshold from its rail. And circuit (g) puts 3*VDD on the drain of an NMOS whose gate is at VDD:
Commit before you compute: what does Diode clamp & the gate limit (g) come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Why the 3*VDD does not help
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. The NMOS conducts only while VGS > VTHN.
28. Diode clamp & the gate limit (g)
Worked example
A diode-connected MOSFET (gate tied to drain) holds its terminal exactly one threshold from its rail. And circuit (g) puts 3*VDD on the drain of an NMOS whose gate is at VDD:
\[ V_A\le V_{gate}-V_{THN}=5-0.8=4.2\,\text{V} \]
Why the 3*VDD does not help
Why: The NMOS conducts only while VGS > VTHN. With the gate pinned at VDD, A stops at VDD - VTHN regardless of how high the drain sits. The 3*VDD just guarantees the drain never starves the device.
\[ \boxed{V_A=V_{DD}-V_{THN}=4.2\,\text{V}} \]
29. Diode clamp & the gate limit (g) — line by line
Picture it
Animation
Shows: Each line of the worked example "Diode clamp & the gate limit (g)", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: The NMOS conducts only while VGS > VTHN. With the gate pinned at VDD, A stops at VDD - VTHN regardless of how high the drain sits. The 3*VDD just guarantees the drain never starves the device.
30. Reading the box symbols: transmission gates
Concept
Circuits (a), (b), (g) draw a transmission gate (TG): a PMOS and an NMOS in parallel, PMOS gate on top (bubble), NMOS gate on the bottom.
In (a) and (b) both signal gates sit at VDD. A TG conducts through whichever device is on: NMOS gate=VDD is on, PMOS gate=VDD is off. So only the NMOS passes - and it follows the NMOS rules (good 0, bad 1). That is why (a)/(b) behave like single NMOS pass gates.
31. Where does each piece belong: HW3 · P4: Voltage at Point A (Baker 10.14)
Sorting
Sort into buckets
These are the pieces of HW3 · P4: Voltage at Point A (Baker 10.14), out of order. Put each one back under the part of the lesson it belongs to.
The clear cases Good vs bad direction
PMOS passing VDD - a good 1 (f); PMOS passing GND - a bad 0 (e)
Diode clamp, series drops & the gate limit
Series pass gates stack the drops; Diode clamp & the gate limit (g); Reading the box symbols: transmission gates
s1
The clear cases Good vs bad direction is where HW3 · P4: Voltage at Point A (Baker 10.14) puts PMOS passing VDD - a good 1 (f), PMOS passing GND - a bad 0 (e). Knowing which part of the lesson a problem belongs to is most of knowing which method to reach for.
s2
Diode clamp, series drops & the gate limit is where HW3 · P4: Voltage at Point A (Baker 10.14) puts Series pass gates stack the drops, Diode clamp & the gate limit (g), Reading the box symbols: transmission gates. Knowing which part of the lesson a problem belongs to is most of knowing which method to reach for.
32. Results for (a)-(g)
Concept
Apply the rulebook to each. The reading (device + what it passes) is shown; the SPICE .op confirms every value.
ckt
reading
VA
(a)
TG, both gates VDD: only NMOS on, passes VDD (1)
4.2 V
(b)
TG, both gates VDD: only NMOS on, passes GND (0)
0 V
(c)
NMOS PG, gate VDD, passes GND (0)
0 V
(d)
NMOS PG, gate VDD, passes VDD (1)
4.2 V
(e)
PMOS PG, gate GND, passes GND (0)
0.9 V
(f)
PMOS PG, gate GND, passes VDD (1)
5 V
(g)
TG off; NMOS from 3*VDD, gate VDD (gate-limited)
4.2 V
Pattern: full rail only in the device's good direction (NMOS->0, PMOS->1); otherwise one threshold short.
33. Fill in: VA for Results for (a)-(g)
Comparison
Comparison matrix
From Results for (a)-(g): refill the VA column from what you know. The rest of the table is as it appeared.
ckt
reading
VA
(a)
TG, both gates VDD: only NMOS on, passes VDD (1)
4.2 V
(b)
TG, both gates VDD: only NMOS on, passes GND (0)
0 V
(c)
NMOS PG, gate VDD, passes GND (0)
0 V
(d)
NMOS PG, gate VDD, passes VDD (1)
4.2 V
(e)
PMOS PG, gate GND, passes GND (0)
0.9 V
(f)
PMOS PG, gate GND, passes VDD (1)
5 V
(g)
TG off; NMOS from 3*VDD, gate VDD (gate-limited)
4.2 V
34. Something is wrong here: the 3*VDD raises A above 4.2 V
Anomaly
Predict first
A student writes this, and it looks reasonable:
Seeing 3*VDD on the NMOS drain in (g) and concluding A swings up toward 15 V.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: An NMOS source-follower-style pass device is controlled by its GATE.
The NMOS high is gate-limited to Vgate - VTHN.
Why: An NMOS source-follower-style pass device is controlled by its GATE. A bigger drain rail cannot lift A past Vgate - VTHN.
35. Trap: the 3*VDD raises A above 4.2 V
Trap
The trap
Seeing 3*VDD on the NMOS drain in (g) and concluding A swings up toward 15 V.
Let the drain rail set A
Why: An NMOS source-follower-style pass device is controlled by its GATE. A bigger drain rail cannot lift A past Vgate - VTHN.
The fix
The NMOS high is gate-limited to Vgate - VTHN.
A = VDD - VTHN = 4.2 V
Why: With the gate at VDD, A tops out at 4.2 V. The 3*VDD only ensures the drain never runs out of headroom - it does not change the ceiling.
36. Which of these survive contact with HW3 · P4: Voltage at Point A (Baker 10.14)?
Two truths and a lie
Sort into buckets
Some of these hold up and some are the exact mistakes this lesson is built to prevent. Sort them.
Holds up
Long-channel Table 9.1. Only two numbers drive every answer here:; The catch: the transistor is only strong in one direction. The other direction loses one threshold. That asymmetry is the entire problem.; Drive an NMOS PG gate to VDD and let it charge A up from its drain. The NMOS conducts only while VGS > VTHN.
Breaks
Reasoning 'the transistor connects A to VDD, so A = 5 V' for an NMOS PG passing a high.; Seeing 3*VDD on the NMOS drain in (g) and concluding A swings up toward 15 V.
sound
These are stated as this lesson states them — each one survives the edge cases HW3 · P4: Voltage at Point A (Baker 10.14) puts it through.
flawed
Each of these is lifted from a trap in this deck: reasonable-sounding, and wrong in a way that only shows up once you rely on it.
37. Check: NMOS passing a high
Check
An NMOS pass gate has gate and drain both tied to VDD = 5 V, source = node A, no load on A. VTHN = 0.8 V. What is VA?
Check your understanding
What voltage does node A settle to?
A. 4.2 V (= VDD - VTHN) (correct)
B. 5 V (= VDD)
C. 0.8 V (= VTHN)
D. 0 V
Answer: A
Why: An NMOS passes a 1 badly. As A charges up, VGS = VDD - A shrinks; when A = VDD - VTHN = 4.2 V, VGS = VTHN and the device shuts off. So A stops one threshold below the rail. (Body effect makes it slightly lower still.)
Why B tempts people
Assumes no threshold drop. That is the PMOS rule (a PMOS passes a good 1). An NMOS loses one VTHN going high.
Why C tempts people
Confuses the threshold itself with the degraded level. The drop is VTHN, so A = VDD - VTHN, not VTHN.
Why D tempts people
That is what the NMOS would deliver passing a LOW (its good direction). Here it passes a high, so A rises to 4.2 V.
38. Check: two NMOS levels in series
Check
An NMOS PG output (VDD - VTHN) drives the GATE of a second NMOS that passes VDD to the final output. VDD = 5 V, VTHN = 0.8 V. What is the final output?
Check your understanding
The final output voltage is:
A. 3.4 V (= VDD - 2*VTHN) (correct)
B. 4.2 V (= VDD - VTHN)
C. 5 V (= VDD)
D. 2.6 V (= VDD - 3*VTHN)
Answer: A
Why: The second NMOS has its gate at VDD - VTHN (not VDD), and an NMOS high is limited to one VTHN below its GATE: output = (VDD - VTHN) - VTHN = VDD - 2*VTHN = 3.4 V. Each threshold-limited stage in series subtracts another VTHN (Lecture 10).
Why B tempts people
That is one drop. Because the second device's gate is already a threshold low, its output drops a second VTHN below that.
Why C tempts people
Full rail would require no drops at all - but every NMOS passing a high (with a gate below VDD here) loses a threshold.
Why D tempts people
Three drops would need a third threshold-limited stage. There are only two here, so it is VDD - 2*VTHN.
39. Connect it up: HW3 · P4: Voltage at Point A (Baker 10.14)
Connect it up
Draw it
One page, no notation unless you need it: draw how these connect — The pass-gate rulebook for point A · The two levels that matter · The MOSFET as a pass gate · Why a pass gate 'gives up' one threshold · Reading the box symbols: transmission gates. Put an arrow wherever one of them is what makes another possible, and label the arrow with why.
40. What you can do now
Recap
NMOS PG: good 0 (A = 0), bad 1 (A = VDD - VTHN = 4.2 V).
PMOS PG: good 1 (A = VDD = 5 V), bad 0 (A = |VTHP| = 0.9 V).
Series threshold-limited stages stack drops (VDD - 2*VTHN); a diode clamps one threshold from its rail.
NMOS high is gate-limited to Vgate - VTHN - even (g)'s 3*VDD drain cannot beat that. Answers: 4.2, 0, 0, 4.2, 0.9, 5, 4.2 V.
Always finish with a SPICE .op: it reports VA directly and confirms each threshold drop. Next in HW3: P5, where these same threshold drops set the VOH and VOL of two inverters.
Sources
R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 4th ed., Problem 10.14 (the MOSFET as a switch; pass gates and threshold drops). — Wiley-IEEE Press, 2019.
ENEE 411 Lecture 10 (Models for Digital Design): the MOSFET pass gate - an NMOS is good at passing a 0, bad at a 1 (passes a 1 with a VTHN drop); a PMOS is good at a 1, bad at a 0 (stops at VTHP). The worked example: one PG gives VDD-VTHN, series PGs give VDD-2VTHN. Notation matched to the course. — Course lecture notes, 2026.
Long-channel Table 9.1: VDD=5V, VTHN=0.8V, |VTHP|=0.9V, so the two degraded levels are VDD-VTHN=4.2V and |VTHP|=0.9V. — Course lecture notes, 2026.
Per-circuit topology from the homework figure: (a),(b),(g) are transmission gates (both signal gates at VDD -> only the NMOS conducts); (c),(d) single NMOS gate=VDD; (e),(f) single PMOS gate=GND. Answers (a)-(g): 4.2, 0, 0, 4.2, 0.9, 5, 4.2 V; SPICE .op confirms. — Author verification, 2026-06-27. Body effect lowers the degraded NMOS high (4.2V) slightly.
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