ENEE 411 Homework 3, Problem 3 (Baker 24.24), rebuilt in full course notation on short-channel Table 9.2 at VDD = 1 V in a 50 nm process. The circuit is three cascaded gain stages with nested-Miller compensation, using Cc1 = 240 f and Cc2. Part (a) finds the open-loop DC gain AOLDC = Av1*Av2*Av3, where each stage contributes roughly gm*Rnode and the intrinsic gain gm*ro is 25 or 50, so the total reaches several thousand - about 74 dB with no load capacitor. It then finds the 3 dB cutoff at each internal node, f3dB,k = 1/(2pi*Rk*Ck) for nodes 1, 2, and 3, where the lowest is the dominant pole, and compares the result with SPICE. Part (b) runs AC and transient analysis with a 100 fF load and demonstrates supply-independent biasing: a self-biased cascode reference holds IVDD nearly constant between VDD = 1 V and 1.2 V in the unity-gain configuration. The 18 slides include block-diagram and nested-Miller figures, three traps, two checks, and a SPICE .op, .ac, and .tran plan.
Subject: Analog CMOS IC Design · 37 slides · diagram-first lesson
Three gain stages in a row. Estimate the open-loop DC gain, find the 3-dB cutoff at every internal node, and show the supply current barely moves when VDD changes from 1 V to 1.2 V.
2. What you will be able to do
Objectives
More stages means more gain - and more poles to manage. By the end you can:
Estimate the open-loop DC gainAOLDC as the product of three stage gains.
Find the 3-dB cutoff at each internal node from that node's own R and C, and pick the dominant pole.
Explain why the VDD supply current stays nearly constant from 1 V to 1.2 V (supply-independent bias).
Write the SPICE.ac and .tran decks (100 fF load, unity-gain follower) that confirm it all.
3. What survived from HW3 · P2: Two-Stage Op-Amp (Baker Example)?
Warm-up
Discussion prompt
Before we open HW3 · P3: Three-Stage Op-Amp (Baker 24.24): without looking back, what was the main idea of HW3 · P2: Two-Stage Op-Amp (Baker Example), and what could you do by the end of it that you could not do before?
Hint: One sentence for the idea, one for the skill. If the second one is blank, that is the part to revisit.
Answer:
ENEE 411 Homework 3, Problem 2: describe the operation of the two-stage Miller op-amp on the short-channel Table 9.2 (VDD=1V, 50nm). Stage 1 = NMOS pair M1/M2 + PMOS active mirror M3/M4 biased by the cascode tail M6T/M6B: the mirror folds both currents (Gm1=gm1), Av1=gm1(ro2||ro4); Stage 2 = PMOS common-source M7 with NMOS cascode sink M8T/M8B, whose high output resistance leaves Rout2~ro7 so Av2=gm7ro7~50 (the PMOS intrinsic gain).
4. Table 9.2 - the short-channel process
Concept
Same 50 nm set as P2 (Lecture 4a, Table 9.2). The thing to remember here is the small intrinsic gain - it forces the design to use three stages.
parameter
NMOS
PMOS
VDD
1 V (also 1.2 V in part b)
same
VTH
0.28 V
0.28 V
gm at ID=10uA
150 uA/V
150 uA/V
ro at ID=10uA
167 kohm
333 kohm
gm*ro (intrinsic gain)
25
50
load cap (part b)
CL = 100 fF
-
The homework directs a device multiplier on the stages; it scales W (hence current and gm) but not the method. Numbers below are estimates from the table - confirm the exact values in SPICE.
5. Fill in: NMOS for Table 9.2 - the short-channel process
Comparison
Comparison matrix
From Table 9.2 - the short-channel process: refill the NMOS column from what you know. The rest of the table is as it appeared.
parameter
NMOS
PMOS
VDD
1 V (also 1.2 V in part b)
same
VTH
0.28 V
0.28 V
gm at ID=10uA
150 uA/V
150 uA/V
ro at ID=10uA
167 kohm
333 kohm
gm*ro (intrinsic gain)
25
50
load cap (part b)
CL = 100 fF
-
6. Three stages, three internal nodes
Concept
Figure (svg): Block diagram of a three-stage amplifier. The input drives gain stage 1 (gain Av1) with output node N1, which drives gain stage 2 (Av2) with output node N2, which drives gain stage 3 (Av3) with output node N3 equals vout, loaded by CL. Each node has its own resistance R and capacitance C to ground, drawn as a parallel RC at N1, N2, and N3. Two nested compensation capacitors are shown: Cc1 from vout back to N1 (outer loop) and Cc2 from vout back to N2 (inner loop).
Three cascaded stages; each node sets one pole. Cc1/Cc2 = nested Miller compensation.
The amplifier is three gain stages in series. Each stage output is a high-impedance node with a resistance Rk (the ros there) and a capacitance Ck (device + wiring; the last node carries CL).
Two facts fall out: the gains multiply, and each node contributes its own pole. Because three poles is hard to stabilize, the design uses two nested compensation caps (Cc1 = 240 fF, Cc2).
7. Why three stages at all?
Intuition
On a 1 V short-channel process the intrinsic gain is tiny - gm*ro = 25 for NMOS, 50 for PMOS. A single common-source stage can't make enough gain for a useful op-amp.
Stack three gain stages and the gains multiply - that is the only way to reach the high open-loop gain feedback needs. The price is two extra poles, which is exactly why the compensation here is more involved than P2's single Cc.
8. Break it if you can: Why three stages at all?
Counterexample
Discussion prompt
On a 1 V short-channel process the intrinsic gain is tiny - gm*ro = 25 for NMOS, 50 for PMOS. A single common-source stage can't make enough gain for a useful op-amp.
That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.
Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.
9. Rebuild the recipe: Recipe: gain & cutoffs of a multi-stage amp
Ranking
Put in order
These are the steps of Recipe: gain & cutoffs of a multi-stage amp, scrambled. Put them back in order before the next slide shows you.
Per-stage gain:Avk = gmk * Rnode,k at each node k.
Open-loop DC gain: multiply them - AOLDC = Av1 * Av2 * Av3.
Per-node cutoff:f3dB,k = 1/(2*pi*Rk*Ck) - one for each internal node.
Dominant pole: the lowest cutoff sets the open-loop bandwidth; the others set the phase margin.
Supply current: trace the self-biased reference; if it is supply-independent, IVDD barely moves with VDD.
Why: This is the order the recipe itself gives. Recalling the sequence without the slide in front of you is the difference between recognising the method and being able to run it — most of what goes wrong in practice is a step done out of turn.
10. Recipe: gain & cutoffs of a multi-stage amp
Pattern
Per-stage gain:Avk = gmk * Rnode,k at each node k.
Open-loop DC gain: multiply them - AOLDC = Av1 * Av2 * Av3.
Per-node cutoff:f3dB,k = 1/(2*pi*Rk*Ck) - one for each internal node.
Dominant pole: the lowest cutoff sets the open-loop bandwidth; the others set the phase margin.
Supply current: trace the self-biased reference; if it is supply-independent, IVDD barely moves with VDD.
11. Where does it stop working: Recipe: gain & cutoffs of a multi-stage amp
Edge cases
Discussion prompt
Recipe: gain & cutoffs of a multi-stage amp works on the cases you have just seen. Push it to the edge: what is the most degenerate input it still handles — empty, zero, one item, everything equal — and what is the first case where it stops being true? Name the case, not just "it breaks".
Hint: Try the smallest legal input, then the largest, then the one where two things collide. Methods are specified at their edges; the middle takes care of itself.
Answer:
Per-stage gain:Avk = gmk * Rnode,k at each node k.
Open-loop DC gain: multiply them - AOLDC = Av1 * Av2 * Av3.
Per-node cutoff:f3dB,k = 1/(2*pi*Rk*Ck) - one for each internal node.
Dominant pole: the lowest cutoff sets the open-loop bandwidth; the others set the phase margin.
Supply current: trace the self-biased reference; if it is supply-independent, IVDD barely moves with VDD.
12. Part (a) Gain & per-node cutoffs
Section
AOLDC and f3dB
13. Guess the shape of the answer: (a) Open-loop DC gain
Estimation
Predict first
Each stage contributes its own gain; cascaded gains multiply:
Commit before you compute: what does (a) Open-loop DC gain come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Multiply three of them
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. AOLDC ~ (a few tens)^3 = several thousand, i.e.
14. (a) Open-loop DC gain
Worked example
Each stage contributes its own gain; cascaded gains multiply:
Why: Each gain stage is on the order of the intrinsic gain. With cascode loading a stage reaches a few tens; take ~17-30 as the per-stage estimate from Table 9.2.
Multiply three of them
Why: AOLDC ~ (a few tens)^3 = several thousand, i.e. roughly 70-80 dB. Cascoding the stages pushes it higher. CONFIRM the exact number in SPICE (.ac, no load cap).
Shows: Each line of the worked example "(a) Open-loop DC gain", appearing one at a time.
The same working the example does, in the order a tutor would write it.
Takeaway: AOLDC ~ (a few tens)^3 = several thousand, i.e. roughly 70-80 dB. Cascoding the stages pushes it higher. CONFIRM the exact number in SPICE (.ac, no load cap).
16. Guess the shape of the answer: (a) The 3-dB cutoff at each node
Estimation
Predict first
Each node is a parallel Rk || Ck to ground - a first-order low-pass. Its cutoff:
Commit before you compute: what does (a) The 3-dB cutoff at each node come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Pick the dominant pole
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. The LOWEST of the three cutoffs is the open-loop dominant pole - usually a high-R internal node or the loaded output.
17. (a) The 3-dB cutoff at each node
Worked example
Figure (svg): One internal node modeled as a parallel RC: a resistor Rk and capacitor Ck from the node to ground. The pole frequency is where the capacitor impedance equals Rk, f equals one over two pi R C.
Every internal node is an RC low-pass - one pole each.
Each node is a parallel Rk || Ck to ground - a first-order low-pass. Its cutoff:
Why: Compute R and C at N1, N2, and N3 (the output, where CL = 100 fF dominates). That gives three cutoff frequencies.
Pick the dominant pole
Why: The LOWEST of the three cutoffs is the open-loop dominant pole - usually a high-R internal node or the loaded output. Compare all three to the SPICE .ac magnitude/phase.
18. Decode the notation: (a) The 3-dB cutoff at each node
Notation
Annotate
From (a) The 3-dB cutoff at each node — read this one piece at a time. What is each part doing?
Compute R and C at N1, N2, and N3 (the output, where CL = 100 fF dominates). That gives three cutoff frequencies.
The LOWEST of the three cutoffs is the open-loop dominant pole - usually a high-R internal node or the loaded output. Compare all three to the SPICE .ac magnitude/phase.
19. (a) Nested Miller compensation
Concept
P2 stabilized two poles with one Cc. Three stages have three poles, so one capacitor isn't enough. This design uses nested Miller: Cc1 wraps the outer two stages, Cc2 wraps the inner pair.
Same idea as P2, applied twice: each cap Miller-multiplies to pull one node's pole down and push another up, herding three poles into a stable, dominant-pole response. The lowest node cutoff from the previous slide is what those caps create.
20. Something is wrong here: one bandwidth for the whole amp
Anomaly
Predict first
A student writes this, and it looks reasonable:
Computing a single f3dB for the amplifier as if it had one RC.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: A three-stage amp has THREE high-impedance nodes, each with its own pole.
Find the cutoff at each node separately, then identify the lowest.
Why: A three-stage amp has THREE high-impedance nodes, each with its own pole. A single-RC estimate hides two of them - and those hidden poles are what threaten stability.
21. Trap: one bandwidth for the whole amp
Trap
The trap
Computing a single f3dB for the amplifier as if it had one RC.
Use one R and one C
Why: A three-stage amp has THREE high-impedance nodes, each with its own pole. A single-RC estimate hides two of them - and those hidden poles are what threaten stability.
The fix
Find the cutoff at each node separately, then identify the lowest.
Compute f3dB at N1, N2, N3
Why: Three nodes = three poles. The problem explicitly asks for the cutoff at each output node; the smallest is the dominant pole and the others tell you the phase margin.
22. Break it on purpose: one bandwidth for the whole amp
Break the constraint
Discussion prompt
The rule this trap just fixed:
Three nodes = three poles. The problem explicitly asks for the cutoff at each output node; the smallest is the dominant pole and the others tell you the phase margin.
Now break it on purpose. Build a case that violates it and follow the consequences until something visibly fails. Where does the failure first show up — and would you have noticed it if you had not been looking?
Hint: The dangerous rules are the ones whose violation still produces an answer. If yours fails loudly, try to find one that fails quietly.
Answer:
A three-stage amp has THREE high-impedance nodes, each with its own pole. A single-RC estimate hides two of them - and those hidden poles are what threaten stability.
23. Part (b) Supply-independent bias
Section
IVDD at 1 V vs 1.2 V
24. (b) Why the supply current barely moves
Intuition
If the bias current came from a plain resistor to VDD, raising VDD from 1 V to 1.2 V would raise the current by 20%. The op-amp's reference (Fig. 20.22) is built not to do that.
It is a self-biased cascode reference: the current is fixed by an internal loop (a matched-device ratio / a VGS over a resistor), not by the rail. The cascode devices give a very high output resistance, so the bias branch looks back into a near-ideal current source:
25. Break it if you can: (b) Why the supply current barely moves
Counterexample
Discussion prompt
If the bias current came from a plain resistor to VDD, raising VDD from 1 V to 1.2 V would raise the current by 20%. The op-amp's reference (Fig. 20.22) is built not to do that.
That is stated as though it always holds. Do one of two things: produce a case where it fails, or say precisely what rules such a case out. "It just does" is not on the menu.
Hint: Hunt at the extremes first — zero, one, negative, empty, equal. If every extreme survives, the reason they survive is the proof.
26. Guess the shape of the answer: (b) Showing it in SPICE
Estimation
Predict first
Put the op-amp in the unity-gain follower configuration shown, drive a small input, and measure the supply current IVDD at two rail voltages:
Commit before you compute: what does (b) Showing it in SPICE come out to? A rough magnitude and the right form is enough — the point is to have something concrete to be wrong about.
Correct: Add AC and transient
Why: A prediction you can defend turns the computation into a check rather than a leap of faith — and an answer that contradicts it is caught on the spot. .ac (1 Hz-1 GHz) confirms AOLDC and the per-node cutoffs from part (a) with the 100 fF load; .tran with a small step shows the follower settling cleanly.
27. (b) Showing it in SPICE
Worked example
Put the op-amp in the unity-gain follower configuration shown, drive a small input, and measure the supply current IVDD at two rail voltages:
VDD
expected IVDD
comment
1.0 V
I_ref (baseline)
set by the internal reference loop
1.2 V
~ same I_ref
cascode keeps it nearly flat
change
a few percent
not the ~20% a resistor would give
The measurement
Why: Run .op at VDD = 1 V, read I(VDD). Repeat at VDD = 1.2 V. The two currents should agree within a few percent - that IS the demonstration the problem asks for.
Add AC and transient
Why: .ac (1 Hz-1 GHz) confirms AOLDC and the per-node cutoffs from part (a) with the 100 fF load; .tran with a small step shows the follower settling cleanly.
28. Fill in: comment for (b) Showing it in SPICE
Comparison
Comparison matrix
From (b) Showing it in SPICE: refill the comment column from what you know. The rest of the table is as it appeared.
VDD
expected IVDD
comment
1.0 V
I_ref (baseline)
set by the internal reference loop
1.2 V
~ same I_ref
cascode keeps it nearly flat
change
a few percent
not the ~20% a resistor would give
29. Something is wrong here: expecting current to track VDD
Anomaly
Predict first
A student writes this, and it looks reasonable:
Assuming IVDD scales with the rail, so 1 V to 1.2 V means 20% more current.
It is wrong. Say what breaks — and say it before you turn the page.
Correct: Only true for a resistor-to-rail.
The current is set by the internal reference, and cascodes shield it from the rail.
Why: Only true for a resistor-to-rail. It ignores that the reference is a self-biased loop feeding cascoded mirrors.
30. Trap: expecting current to track VDD
Trap
The trap
Assuming IVDD scales with the rail, so 1 V to 1.2 V means 20% more current.
Treat the bias like VDD/R
Why: Only true for a resistor-to-rail. It ignores that the reference is a self-biased loop feeding cascoded mirrors.
The fix
The current is set by the internal reference, and cascodes shield it from the rail.
Expect IVDD nearly flat
Why: A self-biased cascode reference fixes the current by a device/resistor ratio, not by VDD. Raising VDD adds headroom, not current - IVDD moves only a few percent.
31. Which of these survive contact with HW3 · P3: Three-Stage Op-Amp (Baker 24.24)?
Two truths and a lie
Sort into buckets
Some of these hold up and some are the exact mistakes this lesson is built to prevent. Sort them.
Holds up
Same 50 nm set as P2 (Lecture 4a, Table 9.2). The thing to remember here is the small intrinsic gain - it forces the design to use three stages.; On a 1 V short-channel process the intrinsic gain is tiny - gm*ro = 25 for NMOS, 50 for PMOS. A single common-source stage can't make enough gain for a useful op-amp.
Breaks
Computing a single f3dB for the amplifier as if it had one RC.; Assuming IVDD scales with the rail, so 1 V to 1.2 V means 20% more current.
sound
These are stated as this lesson states them — each one survives the edge cases HW3 · P3: Three-Stage Op-Amp (Baker 24.24) puts it through.
flawed
Each of these is lifted from a trap in this deck: reasonable-sounding, and wrong in a way that only shows up once you rely on it.
32. Rule out three: Check: open-loop gain of three stages
Elimination
Eliminate the wrong options
Three cascaded stages, each gain ~20. AOLDC is closest to:
3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.
A. ~8000 (78 dB)
B. ~60 (36 dB)
C. ~400 (52 dB)
D. ~20 (26 dB)
Survives elimination: A
Why: Cascaded voltage gains multiply: AOLDC = 202020 = 8000, about 78 dB. Stacking three modest short-channel stages is how you reach a usable open-loop gain on a 1 V process.
33. Check: open-loop gain of three stages
Check
Each of the three stages has a voltage gain of about 20. What is the open-loop DC gain of the whole amplifier?
Check your understanding
Three cascaded stages, each gain ~20. AOLDC is closest to:
A. ~8000 (78 dB) (correct)
B. ~60 (36 dB)
C. ~400 (52 dB)
D. ~20 (26 dB)
Answer: A
Why: Cascaded voltage gains multiply: AOLDC = 202020 = 8000, about 78 dB. Stacking three modest short-channel stages is how you reach a usable open-loop gain on a 1 V process.
Why B tempts people
Added the gains (20+20+20) instead of multiplying. Cascaded stages multiply because each scales the previous output.
Why C tempts people
That is only two stages (20*20). The third stage multiplies in another factor of 20.
Why D tempts people
That is a single stage. The whole point of three stages is to multiply three together.
34. Rule out three: Check: the supply current at 1.2 V
Elimination
Eliminate the wrong options
At VDD = 1.2 V, the supply current IVDD is closest to:
3 of these 4 are wrong. Strike them one at a time, and say what rules each one out before you strike the next. The survivor is the answer.
A. ~50 uA (nearly unchanged)
B. ~60 uA (scales with VDD)
C. ~42 uA (scales inversely with VDD)
D. ~100 uA (doubles)
Survives elimination: A
Why: A self-biased cascode reference sets the current by an internal device/resistor ratio, not by the rail. Raising VDD by 20% adds headroom across the cascodes but leaves the current nearly unchanged - that is the whole point of supply-independent biasing, and exactly what the problem asks you to demonstrate.
35. Check: the supply current at 1.2 V
Check
The op-amp uses a self-biased cascode reference. You measure IVDD = 50 uA at VDD = 1 V. What do you expect at VDD = 1.2 V?
Check your understanding
At VDD = 1.2 V, the supply current IVDD is closest to:
A. ~50 uA (nearly unchanged) (correct)
B. ~60 uA (scales with VDD)
C. ~42 uA (scales inversely with VDD)
D. ~100 uA (doubles)
Answer: A
Why: A self-biased cascode reference sets the current by an internal device/resistor ratio, not by the rail. Raising VDD by 20% adds headroom across the cascodes but leaves the current nearly unchanged - that is the whole point of supply-independent biasing, and exactly what the problem asks you to demonstrate.
Why B tempts people
That is the resistor-to-rail answer (I = VDD/R), which would scale 50 -> 60 uA. The reference is deliberately built to avoid that dependence.
Why C tempts people
There is no inverse-VDD mechanism here; the current is set by the internal loop, not by anything that falls with VDD.
Why D tempts people
Doubling would need the current to depend strongly on VDD. The cascode reference's high output resistance prevents any such large swing.
One page, no notation unless you need it: draw how these connect — Recipe: gain & cutoffs of a multi-stage amp · Table 9.2 - the short-channel process · Three stages, three internal nodes · Why three stages at all? · (a) Nested Miller compensation. Put an arrow wherever one of them is what makes another possible, and label the arrow with why.
37. What you can do now
Recap
*AOLDC = Av1Av2Av3* - three cascaded stage gains multiply (~70-80 dB; SPICE for the exact value).
Each internal node has its own cutoff f3dB,k = 1/(2piRk*Ck); the lowest is the dominant pole.
Nested Miller (Cc1, Cc2) stabilizes the three poles - the same Miller trick as P2, applied twice.
The reference is supply-independent, so IVDD is nearly the same at VDD = 1 V and 1.2 V.
Next in HW3: P4, back to the long-channel process - the threshold-drop (pass-gate) rules that set the voltage at a node behind a single transistor.
Sources
R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 4th ed., Problem 24.24 (three-stage op-amp), bias circuit from Fig. 20.22. — Wiley-IEEE Press, 2019.
ENEE 411 Lecture 8 (op-amps, multistage gain = product of stages) and Lecture 5 (self-biased / supply-independent current references). Notation matched to the course. — Course lecture notes, 2026.
Cascaded-gain product, per-node RC cutoff f=1/(2*pi*R*C), nested-Miller pole structure, and supply-independent (self-biased cascode) reference reasoning. — Author verification, 2026-06-27. Per-stage gain numbers are estimates from the Table 9.2 intrinsic gain; the exact AOLDC and cutoffs come from SPICE (.ac).
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